Update encoding.h for Smrnmi CSR and opcode definitions

riscv/encoding.h

@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (87a8824)
+ * https://github.com/riscv/riscv-opcodes (02b4866)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -72,6 +72,10 @@
 #define USTATUS_UIE         0x00000001
 #define USTATUS_UPIE        0x00000010
 
+#define MNSTATUS_NMIE       0x00000008
+#define MNSTATUS_MNPP       0x00001800
+#define MNSTATUS_MNPV       0x00000080
+
 #define DCSR_XDEBUGVER      (3U<<30)
 #define DCSR_NDRESET        (1<<29)
 #define DCSR_FULLRESET      (1<<28)
@@ -481,10 +485,6 @@
 #define MASK_BINV 0xfe00707f
 #define MATCH_BINVI 0x68001013
 #define MASK_BINVI 0xfc00707f
-#define MATCH_BITREV 0xe6000077
-#define MASK_BITREV 0xfe00707f
-#define MATCH_BITREVI 0xe8000077
-#define MASK_BITREVI 0xfc00707f
 #define MATCH_BLT 0x4063
 #define MASK_BLT 0x707f
 #define MATCH_BLTU 0x6063
@@ -497,8 +497,6 @@
 #define MASK_BMATXOR 0xfe00707f
 #define MATCH_BNE 0x1063
 #define MASK_BNE 0x707f
-#define MATCH_BPICK 0x3077
-#define MASK_BPICK 0x600707f
 #define MATCH_BSET 0x28001033
 #define MASK_BSET 0xfe00707f
 #define MATCH_BSETI 0x28001013
@@ -625,12 +623,6 @@
 #define MASK_CLMULH 0xfe00707f
 #define MATCH_CLMULR 0xa002033
 #define MASK_CLMULR 0xfe00707f
-#define MATCH_CLO16 0xaeb00077
-#define MASK_CLO16 0xfff0707f
-#define MATCH_CLO32 0xafb00077
-#define MASK_CLO32 0xfff0707f
-#define MATCH_CLO8 0xae300077
-#define MASK_CLO8 0xfff0707f
 #define MATCH_CLRS16 0xae800077
 #define MASK_CLRS16 0xfff0707f
 #define MATCH_CLRS32 0xaf800077
@@ -1299,14 +1291,12 @@
 #define MASK_MAX 0xfe00707f
 #define MATCH_MAXU 0xa007033
 #define MASK_MAXU 0xfe00707f
-#define MATCH_MAXW 0xf2000077
-#define MASK_MAXW 0xfe00707f
 #define MATCH_MIN 0xa004033
 #define MASK_MIN 0xfe00707f
 #define MATCH_MINU 0xa005033
 #define MASK_MINU 0xfe00707f
-#define MATCH_MINW 0xf0000077
-#define MASK_MINW 0xfe00707f
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
 #define MATCH_MRET 0x30200073
 #define MASK_MRET 0xffffffff
 #define MATCH_MSUBR32 0xc6001077
@@ -1349,8 +1339,6 @@
 #define MASK_PBSADA 0xfe00707f
 #define MATCH_PKBB16 0xe001077
 #define MASK_PKBB16 0xfe00707f
-#define MATCH_PKBB32 0xe002077
-#define MASK_PKBB32 0xfe00707f
 #define MATCH_PKBT16 0x1e001077
 #define MASK_PKBT16 0xfe00707f
 #define MATCH_PKBT32 0x1e002077
@@ -1361,8 +1349,6 @@
 #define MASK_PKTB32 0xfe00707f
 #define MATCH_PKTT16 0x2e001077
 #define MASK_PKTT16 0xfe00707f
-#define MATCH_PKTT32 0x2e002077
-#define MASK_PKTT32 0xfe00707f
 #define MATCH_PREFETCH_I 0x6013
 #define MASK_PREFETCH_I 0x1f07fff
 #define MATCH_PREFETCH_R 0x106013
@@ -1755,8 +1741,6 @@
 #define MASK_SUNPKD832 0xfff0707f
 #define MATCH_SW 0x2023
 #define MASK_SW 0x707f
-#define MATCH_SWAP8 0xad800077
-#define MASK_SWAP8 0xfff0707f
 #define MATCH_UCLIP16 0x85000077
 #define MASK_UCLIP16 0xff00707f
 #define MATCH_UCLIP32 0xf4000077
@@ -2777,10 +2761,6 @@
 #define MASK_VZEXT_VF4 0xfc0ff07f
 #define MATCH_VZEXT_VF8 0x48012057
 #define MASK_VZEXT_VF8 0xfc0ff07f
-#define MATCH_WEXT 0xce000077
-#define MASK_WEXT 0xfe00707f
-#define MATCH_WEXTI 0xde000077
-#define MASK_WEXTI 0xfe00707f
 #define MATCH_WFI 0x10500073
 #define MASK_WFI 0xffffffff
 #define MATCH_WRS_NTO 0xd00073
@@ -3205,6 +3185,10 @@
 #define CSR_MHPMEVENT29H 0x73d
 #define CSR_MHPMEVENT30H 0x73e
 #define CSR_MHPMEVENT31H 0x73f
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
 #define CSR_MSECCFGH 0x757
 #define CSR_MCYCLEH 0xb80
 #define CSR_MINSTRETH 0xb82
@@ -3415,15 +3399,12 @@ DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
 DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
 DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
-DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV)
-DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI)
 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
 DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
 DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
 DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK)
 DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
 DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
@@ -3487,9 +3468,6 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO)
 DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
 DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
 DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
-DECLARE_INSN(clo16, MATCH_CLO16, MASK_CLO16)
-DECLARE_INSN(clo32, MATCH_CLO32, MASK_CLO32)
-DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8)
 DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16)
 DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32)
 DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8)
@@ -3824,10 +3802,9 @@ DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32)
 DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
 DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
-DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW)
 DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
 DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
-DECLARE_INSN(minw, MATCH_MINW, MASK_MINW)
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
 DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32)
 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
@@ -3849,13 +3826,11 @@ DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
 DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD)
 DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA)
 DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16)
-DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32)
 DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16)
 DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32)
 DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16)
 DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32)
 DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16)
-DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32)
 DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I)
 DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R)
 DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W)
@@ -4052,7 +4027,6 @@ DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830)
 DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831)
 DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832)
 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8)
 DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16)
 DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32)
 DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8)
@@ -4563,8 +4537,6 @@ DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX)
 DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2)
 DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4)
 DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8)
-DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT)
-DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI)
 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
@@ -4975,6 +4947,10 @@ DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H)
 DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H)
 DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H)
 DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H)
+DECLARE_CSR(mnscratch, CSR_MNSCRATCH)
+DECLARE_CSR(mnepc, CSR_MNEPC)
+DECLARE_CSR(mncause, CSR_MNCAUSE)
+DECLARE_CSR(mnstatus, CSR_MNSTATUS)
 DECLARE_CSR(mseccfgh, CSR_MSECCFGH)
 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
 DECLARE_CSR(minstreth, CSR_MINSTRETH)