diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc
index 61fd1644..df86f7cd 100644
--- a/disasm/isa_parser.cc
+++ b/disasm/isa_parser.cc
@@ -70,7 +70,7 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       // G = IMAFD_Zicsr_Zifencei, but Spike includes the latter two
       // unconditionally, so they need not be explicitly added here.
       isa_string = isa_string.substr(0, 4) + "imafd" + isa_string.substr(5);
-      // Fall through
+      [[fallthrough]];
     case 'i':
       extension_table['I'] = true;
       break;
@@ -98,9 +98,9 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
 
     switch (*p) {
       case 'v': vlen = 128; elen = 64; zvf = true; zvd = true;
-                // even rv32iv implies double float
+                [[fallthrough]];
       case 'q': extension_table['D'] = true;
-                // Fall through
+                [[fallthrough]];
       case 'd': extension_table['F'] = true;
     }
     extension_table[toupper(*p)] = true;
diff --git a/riscv/decode.h b/riscv/decode.h
index f36c04e5..d17cb6b0 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -170,23 +170,29 @@ public:
     switch (rvc_rlist()) {
     case 15:
       stack_adj_base += 16;
+      [[fallthrough]];
     case 14:
       if (xlen == 64)
         stack_adj_base += 16;
+      [[fallthrough]];
     case 13:
     case 12:
       stack_adj_base += 16;
+      [[fallthrough]];
     case 11:
     case 10:
       if (xlen == 64)
         stack_adj_base += 16;
+      [[fallthrough]];
     case 9:
     case 8:
       stack_adj_base += 16;
+      [[fallthrough]];
     case 7:
     case 6:
       if (xlen == 64)
         stack_adj_base += 16;
+      [[fallthrough]];
     case 5:
     case 4:
       stack_adj_base += 16;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 428eeb8d..cc868e84 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -222,10 +222,10 @@ void processor_t::set_mmu_capability(int cap)
       break;
     case IMPL_MMU_SV57:
       set_impl(IMPL_MMU_SV57, true);
-      // Fall through
+      [[fallthrough]];
     case IMPL_MMU_SV48:
       set_impl(IMPL_MMU_SV48, true);
-      // Fall through
+      [[fallthrough]];
     case IMPL_MMU_SV39:
       set_impl(IMPL_MMU_SV39, true);
       set_impl(IMPL_MMU, true);
diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index e8cdfb7f..7464f890 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -274,7 +274,10 @@ std::optional<match_result_t> mcontrol_common_t::detect_memory_access_match(proc
 mcontrol_common_t::match_t mcontrol_common_t::legalize_match(reg_t val, reg_t maskmax) noexcept
 {
   switch (val) {
-    case MATCH_NAPOT: if (maskmax == 0) return MATCH_EQUAL;
+    case MATCH_NAPOT:
+      if (maskmax == 0)
+        return MATCH_EQUAL;
+      [[fallthrough]];
     case MATCH_EQUAL:
     case MATCH_GE:
     case MATCH_LT:
diff --git a/softfloat/softfloat.mk.in b/softfloat/softfloat.mk.in
index 0a38404d..850926a6 100644
--- a/softfloat/softfloat.mk.in
+++ b/softfloat/softfloat.mk.in
@@ -252,3 +252,5 @@ softfloat_test_srcs =
 softfloat_install_hdrs = \
 	softfloat.h \
 	softfloat_types.h \
+
+softfloat_CFLAGS = -Wno-implicit-fallthrough