Zicfilp: Set ELP state when executing indirect jumps

riscv/decode_macros.h

@@ -321,3 +321,22 @@ inline long double to_f(float128_t f) { long double r; memcpy(&r, &f, sizeof(r))
   reg_t h##field = get_field(STATE.henvcfg->read(), HENVCFG_##field)
 
 #endif
+
+#define ZICFILP_xLPE(v, prv) \
+  ({ \
+    reg_t lpe = 0ULL; \
+    if (p->extension_enabled(EXT_ZICFILP)) { \
+      DECLARE_XENVCFG_VARS(LPE); \
+      const reg_t msecLPE = get_field(STATE.mseccfg->read(), MSECCFG_MLPE); \
+      switch (prv) { \
+      case PRV_U: lpe = p->extension_enabled('S') ? sLPE : mLPE; break; \
+      case PRV_S: lpe = (v) ? hLPE : mLPE; break; \
+      case PRV_M: lpe = msecLPE; break; \
+      default: abort(); \
+      } \
+    } \
+    lpe; \
+  })
+#define ZICFILP_IS_LP_EXPECTED(reg_num) \
+  (((reg_num) != 1 && (reg_num) != 5 && (reg_num) != 7) ? \
+   elp_t::LP_EXPECTED : elp_t::NO_LP_EXPECTED)

riscv/insns/c_jalr.h

@@ -3,3 +3,7 @@ require(insn.rvc_rs1() != 0);
 reg_t tmp = npc;
 set_pc(RVC_RS1 & ~reg_t(1));
 WRITE_REG(X_RA, tmp);
+
+if (ZICFILP_xLPE(STATE.v, STATE.prv)) {
+  STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rvc_rs1());
+}

riscv/insns/c_jr.h

@@ -1,3 +1,7 @@
 require_extension(EXT_ZCA);
 require(insn.rvc_rs1() != 0);
 set_pc(RVC_RS1 & ~reg_t(1));
+
+if (ZICFILP_xLPE(STATE.v, STATE.prv)) {
+  STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rvc_rs1());
+}

riscv/insns/jalr.h

@@ -1,3 +1,7 @@
 reg_t tmp = npc;
 set_pc((RS1 + insn.i_imm()) & ~reg_t(1));
 WRITE_RD(tmp);
+
+if (ZICFILP_xLPE(STATE.v, STATE.prv)) {
+  STATE.elp = ZICFILP_IS_LP_EXPECTED(insn.rs1());
+}

riscv/processor.cc

@@ -593,6 +593,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   last_inst_priv = 0;
   last_inst_xlen = 0;
   last_inst_flen = 0;
+
+  elp = elp_t::NO_LP_EXPECTED;
 }
 
 void processor_t::set_debug(bool value)

riscv/processor.h

@@ -189,6 +189,8 @@ struct state_t
   reg_t last_inst_priv;
   int last_inst_xlen;
   int last_inst_flen;
+
+  elp_t elp;
 };
 
 // this class represents one processor in a RISC-V machine.