From b60d5766bf1cb3b3162c091cdc6a999f55d340e8 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Tue, 28 Jun 2022 10:27:12 +0800 Subject: [PATCH] add support for zcb --- riscv/decode.h | 3 +++ riscv/insns/c_lbu.h | 2 ++ riscv/insns/c_lh.h | 2 ++ riscv/insns/c_lhu.h | 2 ++ riscv/insns/c_mul.h | 3 +++ riscv/insns/c_not.h | 2 ++ riscv/insns/c_sb.h | 2 ++ riscv/insns/c_sext_b.h | 3 +++ riscv/insns/c_sext_h.h | 3 +++ riscv/insns/c_sh.h | 2 ++ riscv/insns/c_zext_b.h | 2 ++ riscv/insns/c_zext_h.h | 3 +++ riscv/insns/c_zext_w.h | 4 ++++ riscv/riscv.mk.in | 20 +++++++++++++++++++- 14 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 riscv/insns/c_lbu.h create mode 100644 riscv/insns/c_lh.h create mode 100644 riscv/insns/c_lhu.h create mode 100644 riscv/insns/c_mul.h create mode 100644 riscv/insns/c_not.h create mode 100644 riscv/insns/c_sb.h create mode 100644 riscv/insns/c_sext_b.h create mode 100644 riscv/insns/c_sext_h.h create mode 100644 riscv/insns/c_sh.h create mode 100644 riscv/insns/c_zext_b.h create mode 100644 riscv/insns/c_zext_h.h create mode 100644 riscv/insns/c_zext_w.h diff --git a/riscv/decode.h b/riscv/decode.h index 2bf9ddf1..04b453b9 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -117,6 +117,9 @@ public: uint64_t rvc_rs1s() { return 8 + x(7, 3); } uint64_t rvc_rs2s() { return 8 + x(2, 3); } + uint64_t rvc_lbimm() { return (x(5, 1) << 1) + x(6, 1); } + uint64_t rvc_lhimm() { return (x(5, 1) << 1); } + uint64_t v_vm() { return x(25, 1); } uint64_t v_wd() { return x(26, 1); } uint64_t v_nf() { return x(29, 3); } diff --git a/riscv/insns/c_lbu.h b/riscv/insns/c_lbu.h new file mode 100644 index 00000000..e8fb380c --- /dev/null +++ b/riscv/insns/c_lbu.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lbimm())); diff --git a/riscv/insns/c_lh.h b/riscv/insns/c_lh.h new file mode 100644 index 00000000..6a00146c --- /dev/null +++ b/riscv/insns/c_lh.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lhimm())); diff --git a/riscv/insns/c_lhu.h b/riscv/insns/c_lhu.h new file mode 100644 index 00000000..fb190c55 --- /dev/null +++ b/riscv/insns/c_lhu.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lhimm())); diff --git a/riscv/insns/c_mul.h b/riscv/insns/c_mul.h new file mode 100644 index 00000000..3ac0b01b --- /dev/null +++ b/riscv/insns/c_mul.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_either_extension('M', EXT_ZMMUL); +WRITE_RVC_RS1S(sext_xlen(RVC_RS1S * RVC_RS2S)); diff --git a/riscv/insns/c_not.h b/riscv/insns/c_not.h new file mode 100644 index 00000000..26c1626d --- /dev/null +++ b/riscv/insns/c_not.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS1S(sext_xlen(~RVC_RS1S)); diff --git a/riscv/insns/c_sb.h b/riscv/insns/c_sb.h new file mode 100644 index 00000000..5badc28c --- /dev/null +++ b/riscv/insns/c_sb.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +MMU.store(RVC_RS1S + insn.rvc_lbimm(), RVC_RS2S); diff --git a/riscv/insns/c_sext_b.h b/riscv/insns/c_sext_b.h new file mode 100644 index 00000000..dca6af1a --- /dev/null +++ b/riscv/insns/c_sext_b.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBB); +WRITE_RVC_RS1S((sreg_t)(int8_t)(RVC_RS1S)); diff --git a/riscv/insns/c_sext_h.h b/riscv/insns/c_sext_h.h new file mode 100644 index 00000000..b286d076 --- /dev/null +++ b/riscv/insns/c_sext_h.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBB); +WRITE_RVC_RS1S((sreg_t)(int16_t)(RVC_RS1S)); diff --git a/riscv/insns/c_sh.h b/riscv/insns/c_sh.h new file mode 100644 index 00000000..271ca09d --- /dev/null +++ b/riscv/insns/c_sh.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +MMU.store(RVC_RS1S + insn.rvc_lhimm(), RVC_RS2S); diff --git a/riscv/insns/c_zext_b.h b/riscv/insns/c_zext_b.h new file mode 100644 index 00000000..71c518e6 --- /dev/null +++ b/riscv/insns/c_zext_b.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS1S((reg_t)(uint8_t)(RVC_RS1S)); diff --git a/riscv/insns/c_zext_h.h b/riscv/insns/c_zext_h.h new file mode 100644 index 00000000..6b8fd8fb --- /dev/null +++ b/riscv/insns/c_zext_h.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBB); +WRITE_RVC_RS1S((reg_t)(uint16_t)(RVC_RS1S)); diff --git a/riscv/insns/c_zext_w.h b/riscv/insns/c_zext_w.h new file mode 100644 index 00000000..1ad12a4a --- /dev/null +++ b/riscv/insns/c_zext_w.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBA); +require_rv64; +WRITE_RVC_RS1S((reg_t)(uint32_t)(RVC_RS1S)); diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 91f7a5fd..327e9e7e 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1296,6 +1296,23 @@ riscv_insn_svinval = \ hinval_vvma \ hinval_gvma \ +riscv_insn_ext_zcb = \ + c_zext_b \ + c_zext_h \ + c_zext_w \ + c_sext_b \ + c_sext_h \ + c_not \ + c_mul \ + c_lbu \ + c_lhu \ + c_lh \ + c_sb \ + c_sh \ + +riscv_insn_ext_zce = \ + $(riscv_insn_ext_zcb) \ + riscv_insn_ext_cmo = \ cbo_clean \ cbo_flush \ @@ -1312,8 +1329,9 @@ riscv_insn_list = \ $(riscv_insn_ext_zfh) \ $(riscv_insn_ext_q) \ $(riscv_insn_ext_b) \ - $(riscv_insn_ext_k) \ + $(riscv_insn_ext_k) \ $(if $(HAVE_INT128),$(riscv_insn_ext_v),) \ + $(riscv_insn_ext_zce) \ $(riscv_insn_ext_h) \ $(riscv_insn_ext_p) \ $(riscv_insn_priv) \