add support for zcb

riscv/decode.h

@@ -117,6 +117,9 @@ public:
   uint64_t rvc_rs1s() { return 8 + x(7, 3); }
   uint64_t rvc_rs2s() { return 8 + x(2, 3); }
 
+  uint64_t rvc_lbimm() { return (x(5, 1) << 1) + x(6, 1); }
+  uint64_t rvc_lhimm() { return (x(5, 1) << 1); }
+
   uint64_t v_vm() { return x(25, 1); }
   uint64_t v_wd() { return x(26, 1); }
   uint64_t v_nf() { return x(29, 3); }

riscv/insns/c_lbu.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+WRITE_RVC_RS2S(MMU.load<uint8_t>(RVC_RS1S + insn.rvc_lbimm()));

riscv/insns/c_lh.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+WRITE_RVC_RS2S(MMU.load<int16_t>(RVC_RS1S + insn.rvc_lhimm()));

riscv/insns/c_lhu.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+WRITE_RVC_RS2S(MMU.load<uint16_t>(RVC_RS1S + insn.rvc_lhimm()));

riscv/insns/c_mul.h

@@ -0,0 +1,3 @@
+require_extension(EXT_ZCB);
+require_either_extension('M', EXT_ZMMUL);
+WRITE_RVC_RS1S(sext_xlen(RVC_RS1S * RVC_RS2S));

riscv/insns/c_not.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+WRITE_RVC_RS1S(sext_xlen(~RVC_RS1S));

riscv/insns/c_sb.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+MMU.store<uint8_t>(RVC_RS1S + insn.rvc_lbimm(), RVC_RS2S);

riscv/insns/c_sext_b.h

@@ -0,0 +1,3 @@
+require_extension(EXT_ZCB);
+require_extension(EXT_ZBB);
+WRITE_RVC_RS1S((sreg_t)(int8_t)(RVC_RS1S));

riscv/insns/c_sext_h.h

@@ -0,0 +1,3 @@
+require_extension(EXT_ZCB);
+require_extension(EXT_ZBB);
+WRITE_RVC_RS1S((sreg_t)(int16_t)(RVC_RS1S));

riscv/insns/c_sh.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+MMU.store<uint16_t>(RVC_RS1S + insn.rvc_lhimm(), RVC_RS2S);

riscv/insns/c_zext_b.h

@@ -0,0 +1,2 @@
+require_extension(EXT_ZCB);
+WRITE_RVC_RS1S((reg_t)(uint8_t)(RVC_RS1S));

riscv/insns/c_zext_h.h

@@ -0,0 +1,3 @@
+require_extension(EXT_ZCB);
+require_extension(EXT_ZBB);
+WRITE_RVC_RS1S((reg_t)(uint16_t)(RVC_RS1S));

riscv/insns/c_zext_w.h

@@ -0,0 +1,4 @@
+require_extension(EXT_ZCB);
+require_extension(EXT_ZBA);
+require_rv64;
+WRITE_RVC_RS1S((reg_t)(uint32_t)(RVC_RS1S));

riscv/riscv.mk.in

@@ -1296,6 +1296,23 @@ riscv_insn_svinval = \
 	hinval_vvma \
 	hinval_gvma \
 
+riscv_insn_ext_zcb = \
+	c_zext_b \
+	c_zext_h \
+	c_zext_w \
+	c_sext_b \
+	c_sext_h \
+	c_not \
+	c_mul \
+	c_lbu \
+	c_lhu \
+	c_lh \
+	c_sb \
+	c_sh \
+
+riscv_insn_ext_zce = \
+	$(riscv_insn_ext_zcb) \
+
 riscv_insn_ext_cmo = \
 	cbo_clean \
 	cbo_flush \
@@ -1312,8 +1329,9 @@ riscv_insn_list = \
 	$(riscv_insn_ext_zfh) \
 	$(riscv_insn_ext_q) \
 	$(riscv_insn_ext_b) \
-    $(riscv_insn_ext_k) \
+	$(riscv_insn_ext_k) \
 	$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \
+	$(riscv_insn_ext_zce) \
 	$(riscv_insn_ext_h) \
 	$(riscv_insn_ext_p) \
 	$(riscv_insn_priv) \