From b3dfcf1523122cf1fb907fdb75dcdc4d655b7b06 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 29 Dec 2022 15:55:16 -0800
Subject: [PATCH] Respect --[no-]misaligned command-line flag

---
 riscv/mmu.cc | 14 ++++++--------
 riscv/mmu.h  | 18 +++++++-----------
 2 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index b33e3839..7d11babd 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -220,9 +220,9 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate
     load_slow_path_intrapage(addr, len, bytes, xlate_flags);
   } else {
     bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
-#ifndef RISCV_ENABLE_MISALIGNED
-    throw trap_load_address_misaligned(gva, addr, 0, 0);
-#else
+    if (!is_misaligned_enabled())
+      throw trap_load_address_misaligned(gva, addr, 0, 0);
+
     if (xlate_flags & RISCV_XLATE_LR)
       throw trap_load_access_fault(gva, addr, 0, 0);
 
@@ -230,7 +230,6 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate
     load_slow_path_intrapage(addr, len_page0, bytes, xlate_flags);
     if (len_page0 != len)
       load_slow_path_intrapage(addr + len_page0, len - len_page0, bytes + len_page0, xlate_flags);
-#endif
   }
 
   check_triggers(triggers::OPERATION_LOAD, addr, reg_from_bytes(len, bytes));
@@ -269,9 +268,9 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_
 
   if (addr & (len - 1)) {
     bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
-#ifndef RISCV_ENABLE_MISALIGNED
-    throw trap_store_address_misaligned(gva, addr, 0, 0);
-#else
+    if (!is_misaligned_enabled())
+      throw trap_store_address_misaligned(gva, addr, 0, 0);
+
     if (require_alignment)
       throw trap_store_access_fault(gva, addr, 0, 0);
 
@@ -279,7 +278,6 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_
     store_slow_path_intrapage(addr, len_page0, bytes, xlate_flags, actually_store);
     if (len_page0 != len)
       store_slow_path_intrapage(addr + len_page0, len - len_page0, bytes + len_page0, xlate_flags, actually_store);
-#endif
   } else {
     store_slow_path_intrapage(addr, len, bytes, xlate_flags, actually_store);
   }
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 4cc141f5..8c2bcf44 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -139,20 +139,20 @@ public:
 
   void store_float128(reg_t addr, float128_t val)
   {
-#ifndef RISCV_ENABLE_MISALIGNED
-    if (unlikely(addr & (sizeof(float128_t)-1)))
+    if (unlikely(addr & (sizeof(float128_t)-1)) && !is_misaligned_enabled()) {
       throw trap_store_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0);
-#endif
+    }
+
     store<uint64_t>(addr, val.v[0]);
     store<uint64_t>(addr + 8, val.v[1]);
   }
 
   float128_t load_float128(reg_t addr)
   {
-#ifndef RISCV_ENABLE_MISALIGNED
-    if (unlikely(addr & (sizeof(float128_t)-1)))
+    if (unlikely(addr & (sizeof(float128_t)-1)) && !is_misaligned_enabled()) {
       throw trap_load_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0);
-#endif
+    }
+
     return (float128_t){load<uint64_t>(addr), load<uint64_t>(addr + 8)};
   }
 
@@ -285,11 +285,7 @@ public:
 
   int is_misaligned_enabled()
   {
-#ifdef RISCV_ENABLE_MISALIGNED
-    return 1;
-#else
-    return 0;
-#endif
+    return proc && proc->get_cfg().misaligned;
   }
 
   bool is_target_big_endian()