From b30b11dfefe27c7c4f709df991bd91d5b6c9464c Mon Sep 17 00:00:00 2001
From: tsewei-lin <tse-wei.lin@sifive.com>
Date: Tue, 5 Nov 2024 02:21:24 -0800
Subject: [PATCH] vector: crypto: fix constraint checks for vector-crypto
 instructions These are the changes: - Zvkg (vghsh.vv, vgmul.vv)     - vl must
 be a multiple of EGS=4. (spec p.13)     - Check alignment of vd, vs1, vs2
 with lmul - Zvksh (vsm3c.vi, vsm3me.vv)     - vstart, vl must be multiple of
 EGS=4 (spec p.17)     - Check alignment of vd, vs1, vs2 with lmul - Zvksed
 (vsm4k.[vi,vs,vv])     - vstart, vl must be multiple of EGS=4 (spec p.16)    
 - Check alignment of vd, vs1, vs2 with lmul     - For vsm4r.vs, check overlap
 between vs2 and vd (spec p.7) - Zvbb (vwsll.[vv,vx,vi])     - Check alignment
 of vd, vs1, vs2 with lmul	(for widening instructions)     - Check
 overlap between vs2 and vd - Zvkned     - vstart, vl must be multiple of
 EGS=4 (spec p.14)     - Check alignment of vd, vs1, vs2 with lmul     - For
 vaes*.vs, check overlap between vs2 and vd (spec p.7) - Zvknh     - Check
 alignment of vd, vs1, vs2 with lmul

---
 riscv/insns/vghsh_vv.h    |  4 ++++
 riscv/insns/vgmul_vv.h    |  4 ++++
 riscv/insns/vsm3c_vi.h    |  1 +
 riscv/insns/vsm3me_vv.h   |  1 +
 riscv/insns/vsm4k_vi.h    |  1 +
 riscv/insns/vsm4r_vs.h    |  5 ++++-
 riscv/insns/vsm4r_vv.h    |  2 ++
 riscv/insns/vwsll_vi.h    |  1 +
 riscv/insns/vwsll_vv.h    |  1 +
 riscv/insns/vwsll_vx.h    |  1 +
 riscv/zvkned_ext_macros.h | 12 +++++++++++-
 riscv/zvknh_ext_macros.h  |  1 +
 riscv/zvksed_ext_macros.h |  3 +++
 riscv/zvksh_ext_macros.h  |  3 +++
 14 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/riscv/insns/vghsh_vv.h b/riscv/insns/vghsh_vv.h
index bcbfe74f..728678c2 100644
--- a/riscv/insns/vghsh_vv.h
+++ b/riscv/insns/vghsh_vv.h
@@ -2,9 +2,13 @@
 
 #include "zvk_ext_macros.h"
 
+const uint32_t EGS = 4;
+
 require_zvkg;
 require(P.VU.vsew == 32);
 require_egw_fits(128);
+require(P.VU.vl->read() % EGS == 0);
+VI_CHECK_SSS(true)
 
 VI_ZVK_VD_VS1_VS2_EGU32x4_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vgmul_vv.h b/riscv/insns/vgmul_vv.h
index 820b396e..0d223e84 100644
--- a/riscv/insns/vgmul_vv.h
+++ b/riscv/insns/vgmul_vv.h
@@ -2,9 +2,13 @@
 
 #include "zvk_ext_macros.h"
 
+const uint32_t EGS = 4;
+
 require_zvkg;
 require(P.VU.vsew == 32);
 require_egw_fits(128);
+require(P.VU.vl->read() % EGS == 0);
+VI_CHECK_SSS(false)
 
 VI_ZVK_VD_VS2_EGU32x4_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vsm3c_vi.h b/riscv/insns/vsm3c_vi.h
index b3e81216..f9375a54 100644
--- a/riscv/insns/vsm3c_vi.h
+++ b/riscv/insns/vsm3c_vi.h
@@ -3,6 +3,7 @@
 #include "zvksh_ext_macros.h"
 
 require_vsm3_constraints;
+VI_CHECK_SSS(false)
 
 VI_ZVK_VD_VS2_ZIMM5_EGU32x8_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vsm3me_vv.h b/riscv/insns/vsm3me_vv.h
index dd6cb523..388b79fd 100644
--- a/riscv/insns/vsm3me_vv.h
+++ b/riscv/insns/vsm3me_vv.h
@@ -13,6 +13,7 @@
   (ZVKSH_P1((M16) ^  (M9) ^ ZVK_ROL32((M3), 15)) ^ ZVK_ROL32((M13), 7) ^ (M6))
 
 require_vsm3_constraints;
+VI_CHECK_SSS(true)
 
 VI_ZVK_VD_VS1_VS2_EGU32x8_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vsm4k_vi.h b/riscv/insns/vsm4k_vi.h
index 8f52e681..dd6f67d8 100644
--- a/riscv/insns/vsm4k_vi.h
+++ b/riscv/insns/vsm4k_vi.h
@@ -15,6 +15,7 @@ static constexpr uint32_t zvksed_ck[32] = {
 };
 
 require_vsm4_constraints;
+VI_CHECK_SSS(false)
 
 VI_ZVK_VD_VS2_ZIMM5_EGU32x4_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vsm4r_vs.h b/riscv/insns/vsm4r_vs.h
index 44011eb5..649eada9 100644
--- a/riscv/insns/vsm4r_vs.h
+++ b/riscv/insns/vsm4r_vs.h
@@ -2,9 +2,12 @@
 
 #include "zvksed_ext_macros.h"
 
+const uint32_t EGS = 4;
+
 require_vsm4_constraints;
+require_align(insn.rd(), P.VU.vflmul);
 // No overlap of vd and vs2.
-require(insn.rd() != insn.rs2());
+require_noover(insn.rs2(), 1, insn.rd(), P.VU.vflmul);
 
 VI_ZVK_VD_VS2_NOOPERANDS_PRELOOP_EGU32x4_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vsm4r_vv.h b/riscv/insns/vsm4r_vv.h
index 9a18cece..18afee61 100644
--- a/riscv/insns/vsm4r_vv.h
+++ b/riscv/insns/vsm4r_vv.h
@@ -2,7 +2,9 @@
 
 #include "zvksed_ext_macros.h"
 
+
 require_vsm4_constraints;
+VI_CHECK_SSS(false)
 
 VI_ZVK_VD_VS2_EGU32x4_NOVM_LOOP(
   {},
diff --git a/riscv/insns/vwsll_vi.h b/riscv/insns/vwsll_vi.h
index 13b5eb4a..866cd78a 100644
--- a/riscv/insns/vwsll_vi.h
+++ b/riscv/insns/vwsll_vi.h
@@ -3,6 +3,7 @@
 #include "zvk_ext_macros.h"
 
 require_zvbb;
+VI_CHECK_DSS(false);
 
 VI_ZVK_VI_WIDENING_ULOOP({
   const reg_t shift = zimm5 & ((2 * sew) - 1);
diff --git a/riscv/insns/vwsll_vv.h b/riscv/insns/vwsll_vv.h
index 5a64c6c0..180fe974 100644
--- a/riscv/insns/vwsll_vv.h
+++ b/riscv/insns/vwsll_vv.h
@@ -3,6 +3,7 @@
 #include "zvk_ext_macros.h"
 
 require_zvbb;
+VI_CHECK_DSS(true);
 
 VI_ZVK_VV_WIDENING_ULOOP({
   const reg_t shift = (vs1 & ((2 * sew) - 1));
diff --git a/riscv/insns/vwsll_vx.h b/riscv/insns/vwsll_vx.h
index 5264e80e..4137d391 100644
--- a/riscv/insns/vwsll_vx.h
+++ b/riscv/insns/vwsll_vx.h
@@ -3,6 +3,7 @@
 #include "zvk_ext_macros.h"
 
 require_zvbb;
+VI_CHECK_DSS(false);
 
 VI_ZVK_VX_WIDENING_ULOOP({
   const reg_t shift = (rs1 & ((2 * sew) - 1));
diff --git a/riscv/zvkned_ext_macros.h b/riscv/zvkned_ext_macros.h
index db705c71..8ece5687 100644
--- a/riscv/zvkned_ext_macros.h
+++ b/riscv/zvkned_ext_macros.h
@@ -15,10 +15,13 @@
 // is checked in the VI_ZVK_..._EGU32x4_..._LOOP macros.
 #define require_vaes_vs_constraints \
   do { \
+    const uint32_t EGS = 4; \
     require_zvkned; \
+    require(P.VU.vl->read() % EGS == 0); \
     require(P.VU.vsew == 32); \
     require_egw_fits(128); \
-    require(insn.rd() != insn.rs2()); \
+    require_align(insn.rd(), P.VU.vflmul); \
+    require_noover(insn.rs2(), 1, insn.rd(), P.VU.vflmul); \
   } while (false)
 
 // vaes*.vv instruction constraints. Those are the same as the .vs ones,
@@ -30,17 +33,24 @@
 // is checked in the VI_ZVK_..._EGU32x4_..._LOOP macros.
 #define require_vaes_vv_constraints \
   do { \
+    const uint32_t EGS = 4; \
     require_zvkned; \
+    require(P.VU.vl->read() % EGS == 0); \
     require(P.VU.vsew == 32); \
     require_egw_fits(128); \
+    VI_CHECK_SSS(false) \
   } while (false)
 
 // vaeskf*.vi instruction constraints. Those are the same as the .vv ones.
 #define require_vaeskf_vi_constraints \
   do { \
+    const uint32_t EGS = 4; \
     require_zvkned; \
+    require(P.VU.vstart->read() % EGS == 0); \
+    require(P.VU.vl->read() % EGS == 0); \
     require(P.VU.vsew == 32); \
     require_egw_fits(128); \
+    VI_CHECK_SSS(false) \
   } while (false)
 
 #define VAES_XTIME(A) (((A) << 1) ^ (((A) & 0x80) ? 0x1b : 0))
diff --git a/riscv/zvknh_ext_macros.h b/riscv/zvknh_ext_macros.h
index b50818bd..98236b03 100644
--- a/riscv/zvknh_ext_macros.h
+++ b/riscv/zvknh_ext_macros.h
@@ -15,6 +15,7 @@
 // macros.
 #define require_vsha2_common_constraints \
   do { \
+    VI_CHECK_SSS(true) \
     require(P.VU.vsew == 32 || P.VU.vsew == 64); \
     require(insn.rd() != insn.rs1()); \
     require(insn.rd() != insn.rs2()); \
diff --git a/riscv/zvksed_ext_macros.h b/riscv/zvksed_ext_macros.h
index 46e399b9..3ffa2720 100644
--- a/riscv/zvksed_ext_macros.h
+++ b/riscv/zvksed_ext_macros.h
@@ -16,9 +16,12 @@
 // is checked in the VI_ZVK_..._EGU32x4_..._LOOP macros.
 #define require_vsm4_constraints \
   do { \
+    const uint32_t EGS = 4; \
     require_zvksed; \
     require(P.VU.vsew == 32); \
     require_egw_fits(128); \
+    require(P.VU.vstart->read() % EGS == 0); \
+    require(P.VU.vl->read() % EGS == 0); \
   } while (false)
 
 // Returns a uint32_t value constructed from the 4 bytes (uint8_t)
diff --git a/riscv/zvksh_ext_macros.h b/riscv/zvksh_ext_macros.h
index 71c5a091..c4549da2 100644
--- a/riscv/zvksh_ext_macros.h
+++ b/riscv/zvksh_ext_macros.h
@@ -16,9 +16,12 @@
 // is checked in the VI_ZVK_..._EGU32x8_..._LOOP macros.
 #define require_vsm3_constraints \
   do { \
+    const uint32_t EGS = 8; \
     require_zvksh; \
     require(P.VU.vsew == 32); \
     require_egw_fits(256); \
+    require(P.VU.vstart->read() % EGS == 0); \
+    require(P.VU.vl->read() % EGS == 0); \
     require(insn.rd() != insn.rs2()); \
   } while (false)