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riscv-isa-sim
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Change address used in gdb debug example. 

PR #889 put a UART at 0x10000000, which conflicts with the old address.
Fixes #1179.
pull/1196/head
Tim Newsome 4 years ago
parent
c94cafa66a
commit
b282cafd59
1 changed files with 3 additions and 3 deletions
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      README.md

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README.md
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@ -233,7 +233,7 @@ OUTPUT_ARCH( "riscv" )
SECTIONS SECTIONS
{ {
. = 0x10010000; . = 0x10110000;
.text : { *(.text) } .text : { *(.text) }
.data : { *(.data) } .data : { *(.data) }
} }
@ -243,7 +243,7 @@ $ riscv64-unknown-elf-gcc -g -Og -T spike.lds -nostartfiles -o rot13-64 rot13-64
To debug this program, first run spike telling it to listen for OpenOCD: To debug this program, first run spike telling it to listen for OpenOCD:
``` ```
$ spike --rbb-port=9824 -m0x10000000:0x20000 rot13-64 $ spike --rbb-port=9824 -m0x10100000:0x20000 rot13-64
Listening for remote bitbang connection on port 9824. Listening for remote bitbang connection on port 9824.
``` ```
@ -299,7 +299,7 @@ $2 = 0
(gdb) print text (gdb) print text
$3 = "Vafgehpgvba frgf jnag gb or serr!" $3 = "Vafgehpgvba frgf jnag gb or serr!"
(gdb) b done (gdb) b done
Breakpoint 1 at 0x10010064: file rot13.c, line 22. Breakpoint 1 at 0x10110064: file rot13.c, line 22.
(gdb) c (gdb) c
Continuing. Continuing.
Disabling abstract command writes to CSRs. Disabling abstract command writes to CSRs.

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