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riscv-isa-sim
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Merge pull request #2246 from chihminchao/rvp-rv32-rv64 

rvp for rv32/rv64
pull/2288/head
Andrew Waterman 3 months ago
committed by GitHub
parent
632777d371 f2aa295a31
commit
b21cccdc5f
No known key found for this signature in database GPG Key ID: B5690EEEBB952194
617 changed files with 7353 additions and 18 deletions
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  1. 791
      disasm/disasm.cc
  2. 16
      riscv/decode.h
  3. 19
      riscv/decode_macros.h
  4. 1836
      riscv/encoding.h
  5. 1
      riscv/insn_template.h
  6. 3
      riscv/insns/aadd.h
  7. 3
      riscv/insns/aaddu.h
  8. 4
      riscv/insns/abs.h
  9. 5
      riscv/insns/absw.h
  10. 3
      riscv/insns/addd.h
  11. 3
      riscv/insns/asub.h
  12. 3
      riscv/insns/asubu.h
  13. 10
      riscv/insns/cls.h
  14. 11
      riscv/insns/clsw.h
  15. 3
      riscv/insns/macc_h00.h
  16. 3
      riscv/insns/macc_h01.h
  17. 3
      riscv/insns/macc_h11.h
  18. 3
      riscv/insns/macc_w00.h
  19. 3
      riscv/insns/macc_w01.h
  20. 3
      riscv/insns/macc_w11.h
  21. 3
      riscv/insns/maccsu_h00.h
  22. 3
      riscv/insns/maccsu_h11.h
  23. 3
      riscv/insns/maccsu_w00.h
  24. 3
      riscv/insns/maccsu_w11.h
  25. 3
      riscv/insns/maccu_h00.h
  26. 3
      riscv/insns/maccu_h01.h
  27. 3
      riscv/insns/maccu_h11.h
  28. 3
      riscv/insns/maccu_w00.h
  29. 3
      riscv/insns/maccu_w01.h
  30. 3
      riscv/insns/maccu_w11.h
  31. 2
      riscv/insns/merge.h
  32. 4
      riscv/insns/mhacc.h
  33. 4
      riscv/insns/mhacc_h0.h
  34. 4
      riscv/insns/mhacc_h1.h
  35. 4
      riscv/insns/mhaccsu.h
  36. 4
      riscv/insns/mhaccsu_h0.h
  37. 4
      riscv/insns/mhaccsu_h1.h
  38. 4
      riscv/insns/mhaccu.h
  39. 5
      riscv/insns/mhracc.h
  40. 5
      riscv/insns/mhraccsu.h
  41. 5
      riscv/insns/mhraccu.h
  42. 3
      riscv/insns/mqacc_h00.h
  43. 3
      riscv/insns/mqacc_h01.h
  44. 3
      riscv/insns/mqacc_h11.h
  45. 3
      riscv/insns/mqacc_w00.h
  46. 3
      riscv/insns/mqacc_w01.h
  47. 3
      riscv/insns/mqacc_w11.h
  48. 3
      riscv/insns/mqracc_h00.h
  49. 3
      riscv/insns/mqracc_h01.h
  50. 3
      riscv/insns/mqracc_h11.h
  51. 3
      riscv/insns/mqracc_w00.h
  52. 3
      riscv/insns/mqracc_w01.h
  53. 3
      riscv/insns/mqracc_w11.h
  54. 3
      riscv/insns/mqrwacc.h
  55. 3
      riscv/insns/mqwacc.h
  56. 3
      riscv/insns/mseq.h
  57. 3
      riscv/insns/mslt.h
  58. 3
      riscv/insns/msltu.h
  59. 3
      riscv/insns/mul_h00.h
  60. 3
      riscv/insns/mul_h01.h
  61. 3
      riscv/insns/mul_h11.h
  62. 3
      riscv/insns/mul_w00.h
  63. 3
      riscv/insns/mul_w01.h
  64. 3
      riscv/insns/mul_w11.h
  65. 4
      riscv/insns/mulh_h0.h
  66. 4
      riscv/insns/mulh_h1.h
  67. 4
      riscv/insns/mulhr.h
  68. 4
      riscv/insns/mulhrsu.h
  69. 4
      riscv/insns/mulhru.h
  70. 4
      riscv/insns/mulhsu_h0.h
  71. 4
      riscv/insns/mulhsu_h1.h
  72. 8
      riscv/insns/mulq.h
  73. 8
      riscv/insns/mulqr.h
  74. 3
      riscv/insns/mulsu_h00.h
  75. 3
      riscv/insns/mulsu_h11.h
  76. 3
      riscv/insns/mulsu_w00.h
  77. 3
      riscv/insns/mulsu_w11.h
  78. 3
      riscv/insns/mulu_h00.h
  79. 3
      riscv/insns/mulu_h01.h
  80. 3
      riscv/insns/mulu_h11.h
  81. 3
      riscv/insns/mulu_w00.h
  82. 3
      riscv/insns/mulu_w01.h
  83. 3
      riscv/insns/mulu_w11.h
  84. 2
      riscv/insns/mvm.h
  85. 2
      riscv/insns/mvmn.h
  86. 5
      riscv/insns/nclip.h
  87. 5
      riscv/insns/nclipi.h
  88. 5
      riscv/insns/nclipiu.h
  89. 11
      riscv/insns/nclipr.h
  90. 11
      riscv/insns/nclipri.h
  91. 11
      riscv/insns/nclipriu.h
  92. 11
      riscv/insns/nclipru.h
  93. 5
      riscv/insns/nclipu.h
  94. 3
      riscv/insns/nsra.h
  95. 3
      riscv/insns/nsrai.h
  96. 11
      riscv/insns/nsrar.h
  97. 11
      riscv/insns/nsrari.h
  98. 3
      riscv/insns/nsrl.h
  99. 3
      riscv/insns/nsrli.h
  100. 3
      riscv/insns/paadd_b.h

791
disasm/disasm.cc
View File

@ -121,6 +121,25 @@ struct : public arg_t {
}
} xrs3;
// RV32 P-extension register pair arguments (even register number)
struct : public arg_t {
std::string to_string(insn_t insn) const {
return xpr_name[insn.rd_p()];
}
} xrd_p;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return xpr_name[insn.rs1_p()];
}
} xrs1_p;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return xpr_name[insn.rs2_p()];
}
} xrs2_p;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return frm_name(insn.rm());
@ -538,33 +557,51 @@ struct : public arg_t {
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm2());
return std::to_string((int)insn.p_imm8());
}
} p_imm8;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm10csl());
}
} p_imm10csl;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm10csr());
}
} p_imm2;
} p_imm10csr;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm3());
return std::to_string((int)insn.p_imm10csrw());
}
} p_imm3;
} p_imm10csrw;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm4());
return std::to_string((int)insn.shamtd());
}
} p_imm4;
} shamtd;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm5());
return std::to_string((int)insn.shamtw());
}
} p_imm5;
} shamtw;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.p_imm6());
return std::to_string((int)insn.shamth());
}
} p_imm6;
} shamth;
struct : public arg_t {
std::string to_string(insn_t insn) const {
return std::to_string((int)insn.shamtb());
}
} shamtb;
struct : public arg_t {
std::string to_string(insn_t insn) const {
@ -617,6 +654,44 @@ static void NOINLINE add_r3type_insn(disassembler_t* d, const char* name, uint32
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &xrs2, &xrs3}));
}
// RV32 P-extension register pair instruction types
// Type 1: rdp only (widening: result is pair, sources are normal regs)
static void NOINLINE add_rtype_rdp_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd_p, &xrs1, &xrs2}));
}
// Type 1 variant: rdp + rs1 only (for unary widening ops)
static void NOINLINE add_r1type_rdp_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd_p, &xrs1}));
}
// Type 1 variant: rdp + rs1 + imm (for widening immediate ops)
// Type 2: rs1p only (narrowing: source is pair, result is normal reg)
static void NOINLINE add_rtype_rs1p_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1_p, &xrs2}));
}
// Type 3: rdp + rs1p (both pairs, with scalar rs2)
static void NOINLINE add_rtype_rdp_rs1p_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd_p, &xrs1_p, &xrs2}));
}
// Type 3 variant: rdp + rs1p only (for unary doubleword ops)
static void NOINLINE add_r1type_rdp_rs1p_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd_p, &xrs1_p}));
}
// Type 4: rdp + rs1p + rs2p (all three are register pairs)
static void NOINLINE add_rtype_pair_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd_p, &xrs1_p, &xrs2_p}));
}
static void NOINLINE add_itype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
{
d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &imm}));
@ -859,6 +934,19 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
#define DEFINE_R3TYPE(code) add_r3type_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE(code) add_itype_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_SHIFT(code) add_itype_shift_insn(this, #code, match_##code, mask_##code);
// RV32 P-extension register pair macros
#define DEFINE_RTYPE_RDP(code) add_rtype_rdp_insn(this, #code, match_##code, mask_##code);
#define DEFINE_R1TYPE_RDP(code) add_r1type_rdp_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_RDP(code) add_itype_rdp_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_SHIFT_RDP(code) add_itype_shift_rdp_insn(this, #code, match_##code, mask_##code);
#define DEFINE_RTYPE_RS1P(code) add_rtype_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_RS1P(code) add_itype_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_SHIFT_RS1P(code) add_itype_shift_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_RTYPE_RDP_RS1P(code) add_rtype_rdp_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_R1TYPE_RDP_RS1P(code) add_r1type_rdp_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_RDP_RS1P(code) add_itype_rdp_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_ITYPE_SHIFT_RDP_RS1P(code) add_itype_shift_rdp_rs1p_insn(this, #code, match_##code, mask_##code);
#define DEFINE_RTYPE_PAIR(code) add_rtype_pair_insn(this, #code, match_##code, mask_##code);
#define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
#define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
#define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
@ -2304,6 +2392,689 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
DISASM_INSN("c.sspopchk", c_sspopchk_x5, 0, {&rvc_t0});
}
}
// P-extension (Packed SIMD) instructions
if (ext_enabled('P')) {
// R-type instructions (rd, rs1, rs2) - RV32 only (share opcode with RV64 packed-word)
if (xlen_eq(32)) {
DEFINE_RTYPE(aadd);
DEFINE_RTYPE(aaddu);
DEFINE_RTYPE(asub);
DEFINE_RTYPE(asubu);
DEFINE_RTYPE(mseq);
DEFINE_RTYPE(mslt);
DEFINE_RTYPE(msltu);
}
// RV32/RV64 common instructions
DEFINE_RTYPE_PAIR(addd);
DEFINE_RTYPE_PAIR(subd);
DEFINE_RTYPE(merge);
DEFINE_RTYPE(mvm);
DEFINE_RTYPE(mvmn);
// Type 2: rs1p - Narrowing instructions (rd normal, rs1p is pair, rs2 normal/scalar)
DEFINE_RTYPE_RS1P(nclip);
DEFINE_RTYPE_RS1P(nclipr);
DEFINE_RTYPE_RS1P(nclipu);
DEFINE_RTYPE_RS1P(nclipru);
DEFINE_RTYPE_RS1P(nsra);
DEFINE_RTYPE_RS1P(nsrar);
DEFINE_RTYPE_RS1P(nsrl);
// RV32-only instructions (share opcode with RV64 packed-word)
if (xlen_eq(32)) {
DEFINE_RTYPE(sadd);
DEFINE_RTYPE(saddu);
DEFINE_RTYPE(ssub);
DEFINE_RTYPE(ssubu);
DEFINE_RTYPE(ssh1sadd);
DEFINE_RTYPE(ssha);
DEFINE_RTYPE(sshar);
DEFINE_RTYPE(sshl);
DEFINE_RTYPE(sshlr);
}
DEFINE_RTYPE_PAIR(sha);
DEFINE_RTYPE_PAIR(shar);
DEFINE_RTYPE(slx);
DEFINE_RTYPE(srx);
// Type 1: rdp - Widening instructions (rdp is pair, rs1/rs2 normal)
DEFINE_RTYPE_RDP(wadd);
DEFINE_RTYPE_RDP(wadda);
DEFINE_RTYPE_RDP(waddu);
DEFINE_RTYPE_RDP(waddau);
DEFINE_RTYPE_RDP(wsub);
DEFINE_RTYPE_RDP(wsuba);
DEFINE_RTYPE_RDP(wsubu);
DEFINE_RTYPE_RDP(wsubau);
DEFINE_RTYPE_RDP(wsll);
DEFINE_RTYPE_RDP(wsla);
DEFINE_RTYPE_RDP(wmul);
DEFINE_RTYPE_RDP(wmulu);
DEFINE_RTYPE_RDP(wmulsu);
DEFINE_RTYPE_RDP(wmacc);
DEFINE_RTYPE_RDP(wmaccu);
DEFINE_RTYPE_RDP(wmaccsu);
// R-type mac/mul instructions with element selection (RV32 only - share opcode with RV64 packed-word)
if (xlen_eq(32)) {
DEFINE_RTYPE(macc_h00);
DEFINE_RTYPE(macc_h01);
DEFINE_RTYPE(macc_h11);
DEFINE_RTYPE(maccu_h00);
DEFINE_RTYPE(maccu_h01);
DEFINE_RTYPE(maccu_h11);
DEFINE_RTYPE(maccsu_h00);
DEFINE_RTYPE(maccsu_h11);
DEFINE_RTYPE(mul_h00);
DEFINE_RTYPE(mul_h01);
DEFINE_RTYPE(mul_h11);
DEFINE_RTYPE(mulu_h00);
DEFINE_RTYPE(mulu_h01);
DEFINE_RTYPE(mulu_h11);
DEFINE_RTYPE(mulsu_h00);
DEFINE_RTYPE(mulsu_h11);
DEFINE_RTYPE(mulh_h0);
DEFINE_RTYPE(mulh_h1);
DEFINE_RTYPE(mulhsu_h0);
DEFINE_RTYPE(mulhsu_h1);
DEFINE_RTYPE(mulhr);
DEFINE_RTYPE(mulhru);
DEFINE_RTYPE(mulhrsu);
DEFINE_RTYPE(mulq);
DEFINE_RTYPE(mulqr);
DEFINE_RTYPE(mhacc);
DEFINE_RTYPE(mhaccu);
DEFINE_RTYPE(mhaccsu);
DEFINE_RTYPE(mhacc_h0);
DEFINE_RTYPE(mhacc_h1);
DEFINE_RTYPE(mhaccsu_h0);
DEFINE_RTYPE(mhaccsu_h1);
DEFINE_RTYPE(mhracc);
DEFINE_RTYPE(mhraccu);
DEFINE_RTYPE(mhraccsu);
}
DEFINE_RTYPE(mqacc_h00);
DEFINE_RTYPE(mqacc_h01);
DEFINE_RTYPE(mqacc_h11);
DEFINE_RTYPE(mqracc_h00);
DEFINE_RTYPE(mqracc_h01);
DEFINE_RTYPE(mqracc_h11);
// R1-type instructions (rd, rs1) - unary ops
DEFINE_R1TYPE(abs);
DEFINE_R1TYPE(cls);
// I-type shift instructions (rd, rs1, shamt)
DISASM_INSN("nclipi", nclipi, 0, {&xrd, &xrs1, &shamtd});
DISASM_INSN("nclipiu", nclipiu, 0, {&xrd, &xrs1, &shamtd});
DISASM_INSN("nclipri", nclipri, 0, {&xrd, &xrs1, &shamtd});
DISASM_INSN("nclipriu", nclipriu, 0, {&xrd, &xrs1, &shamtd});
DISASM_INSN("nsrai", nsrai, 0, {&xrd, &xrs1, &shamtd});
DISASM_INSN("nsrari", nsrari, 0, {&xrd, &xrs1, &shamtd});
DISASM_INSN("nsrli", nsrli, 0, {&xrd, &xrs1, &shamtd});
// sslai shares opcode with psslai_w on RV64
if (xlen_eq(32)) {
DISASM_INSN("sslai", sslai, 0, {&xrd, &xrs1, &shamt});
}
DISASM_INSN("wslli", wslli, 0, {&xrd, &xrs1, &shamt});
DISASM_INSN("wslai", wslai, 0, {&xrd, &xrs1, &shamt});
if (xlen_eq(64)) {
DISASM_INSN("sati", sati, 0, {&xrd, &xrs1, &shamt});
DISASM_INSN("usati", usati, 0, {&xrd, &xrs1, &shamt});
DISASM_INSN("srari", srari, 0, {&xrd, &xrs1, &shamt});
} else {
DISASM_INSN("sati", sati_rv32, 0, {&xrd, &xrs1, &shamt});
DISASM_INSN("usati", usati_rv32, 0, {&xrd, &xrs1, &shamt});
DISASM_INSN("srari", srari_rv32, 0, {&xrd, &xrs1, &shamt});
}
// Packed R-type instructions (rd, rs1, rs2) - RV32/RV64 common
DEFINE_RTYPE(paadd_b);
DEFINE_RTYPE(paadd_h);
// Type 4: rdp + rs1p + rs2p - Doubleword pair-to-pair ops
DEFINE_RTYPE_PAIR(paadd_db);
DEFINE_RTYPE_PAIR(paadd_dh);
DEFINE_RTYPE_PAIR(paadd_dw);
DEFINE_RTYPE(paaddu_b);
DEFINE_RTYPE(paaddu_h);
DEFINE_RTYPE_PAIR(paaddu_db);
DEFINE_RTYPE_PAIR(paaddu_dh);
DEFINE_RTYPE_PAIR(paaddu_dw);
DEFINE_RTYPE(paas_hx);
DEFINE_RTYPE_PAIR(paas_dhx);
DEFINE_RTYPE(pabd_b);
DEFINE_RTYPE(pabd_h);
DEFINE_RTYPE_PAIR(pabd_db);
DEFINE_RTYPE_PAIR(pabd_dh);
DEFINE_RTYPE(pabdu_b);
DEFINE_RTYPE(pabdu_h);
DEFINE_RTYPE_PAIR(pabdu_db);
DEFINE_RTYPE_PAIR(pabdu_dh);
DEFINE_RTYPE(pabdsumu_b);
DEFINE_RTYPE(pabdsumau_b);
DEFINE_RTYPE(padd_b);
DEFINE_RTYPE(padd_h);
DEFINE_RTYPE(padd_bs);
DEFINE_RTYPE(padd_hs);
DEFINE_RTYPE_PAIR(padd_db);
DEFINE_RTYPE_PAIR(padd_dh);
DEFINE_RTYPE_PAIR(padd_dw);
// Type 3: rdp + rs1p - Doubleword with scalar rs2
DEFINE_RTYPE_RDP_RS1P(padd_dbs);
DEFINE_RTYPE_RDP_RS1P(padd_dhs);
DEFINE_RTYPE_RDP_RS1P(padd_dws);
DEFINE_RTYPE(pasub_b);
DEFINE_RTYPE(pasub_h);
DEFINE_RTYPE_PAIR(pasub_db);
DEFINE_RTYPE_PAIR(pasub_dh);
DEFINE_RTYPE_PAIR(pasub_dw);
DEFINE_RTYPE(pasubu_b);
DEFINE_RTYPE(pasubu_h);
DEFINE_RTYPE_PAIR(pasubu_db);
DEFINE_RTYPE_PAIR(pasubu_dh);
DEFINE_RTYPE_PAIR(pasubu_dw);
DEFINE_RTYPE(pasa_hx);
DEFINE_RTYPE_PAIR(pasa_dhx);
DEFINE_RTYPE(pas_hx);
DEFINE_RTYPE_PAIR(pas_dhx);
DEFINE_RTYPE(psadd_b);
DEFINE_RTYPE(psadd_h);
DEFINE_RTYPE_PAIR(psadd_db);
DEFINE_RTYPE_PAIR(psadd_dh);
DEFINE_RTYPE_PAIR(psadd_dw);
DEFINE_RTYPE(psaddu_b);
DEFINE_RTYPE(psaddu_h);
DEFINE_RTYPE_PAIR(psaddu_db);
DEFINE_RTYPE_PAIR(psaddu_dh);
DEFINE_RTYPE_PAIR(psaddu_dw);
DEFINE_RTYPE(psub_b);
DEFINE_RTYPE(psub_h);
DEFINE_RTYPE_PAIR(psub_db);
DEFINE_RTYPE_PAIR(psub_dh);
DEFINE_RTYPE_PAIR(psub_dw);
DEFINE_RTYPE(pssub_b);
DEFINE_RTYPE(pssub_h);
DEFINE_RTYPE_PAIR(pssub_db);
DEFINE_RTYPE_PAIR(pssub_dh);
DEFINE_RTYPE_PAIR(pssub_dw);
DEFINE_RTYPE(pssubu_b);
DEFINE_RTYPE(pssubu_h);
DEFINE_RTYPE_PAIR(pssubu_db);
DEFINE_RTYPE_PAIR(pssubu_dh);
DEFINE_RTYPE_PAIR(pssubu_dw);
DEFINE_RTYPE(psa_hx);
DEFINE_RTYPE_PAIR(psa_dhx);
DEFINE_RTYPE(psas_hx);
DEFINE_RTYPE_PAIR(psas_dhx);
DEFINE_RTYPE(pssa_hx);
DEFINE_RTYPE_PAIR(pssa_dhx);
DEFINE_RTYPE(pmax_b);
DEFINE_RTYPE(pmax_h);
DEFINE_RTYPE_PAIR(pmax_db);
DEFINE_RTYPE_PAIR(pmax_dh);
DEFINE_RTYPE_PAIR(pmax_dw);
DEFINE_RTYPE(pmaxu_b);
DEFINE_RTYPE(pmaxu_h);
DEFINE_RTYPE_PAIR(pmaxu_db);
DEFINE_RTYPE_PAIR(pmaxu_dh);
DEFINE_RTYPE_PAIR(pmaxu_dw);
DEFINE_RTYPE(pmin_b);
DEFINE_RTYPE(pmin_h);
DEFINE_RTYPE_PAIR(pmin_db);
DEFINE_RTYPE_PAIR(pmin_dh);
DEFINE_RTYPE_PAIR(pmin_dw);
DEFINE_RTYPE(pminu_b);
DEFINE_RTYPE(pminu_h);
DEFINE_RTYPE_PAIR(pminu_db);
DEFINE_RTYPE_PAIR(pminu_dh);
DEFINE_RTYPE_PAIR(pminu_dw);
DEFINE_RTYPE(pmseq_b);
DEFINE_RTYPE(pmseq_h);
DEFINE_RTYPE_PAIR(pmseq_db);
DEFINE_RTYPE_PAIR(pmseq_dh);
DEFINE_RTYPE_PAIR(pmseq_dw);
DEFINE_RTYPE(pmslt_b);
DEFINE_RTYPE(pmslt_h);
DEFINE_RTYPE_PAIR(pmslt_db);
DEFINE_RTYPE_PAIR(pmslt_dh);
DEFINE_RTYPE_PAIR(pmslt_dw);
DEFINE_RTYPE(pmsltu_b);
DEFINE_RTYPE(pmsltu_h);
DEFINE_RTYPE_PAIR(pmsltu_db);
DEFINE_RTYPE_PAIR(pmsltu_dh);
DEFINE_RTYPE_PAIR(pmsltu_dw);
DEFINE_RTYPE(psll_bs);
DEFINE_RTYPE(psll_hs);
// Type 3: rdp + rs1p - Doubleword shift with scalar rs2
DEFINE_RTYPE_RDP_RS1P(psll_dbs);
DEFINE_RTYPE_RDP_RS1P(psll_dhs);
DEFINE_RTYPE_RDP_RS1P(psll_dws);
DEFINE_RTYPE(psra_bs);
DEFINE_RTYPE(psra_hs);
DEFINE_RTYPE_RDP_RS1P(psra_dbs);
DEFINE_RTYPE_RDP_RS1P(psra_dhs);
DEFINE_RTYPE_RDP_RS1P(psra_dws);
DEFINE_RTYPE(psrl_bs);
DEFINE_RTYPE(psrl_hs);
DEFINE_RTYPE_RDP_RS1P(psrl_dbs);
DEFINE_RTYPE_RDP_RS1P(psrl_dhs);
DEFINE_RTYPE_RDP_RS1P(psrl_dws);
DEFINE_RTYPE(pssha_hs);
DEFINE_RTYPE_RDP_RS1P(pssha_dhs);
DEFINE_RTYPE_RDP_RS1P(pssha_dws);
DEFINE_RTYPE(psshar_hs);
DEFINE_RTYPE_RDP_RS1P(psshar_dhs);
DEFINE_RTYPE_RDP_RS1P(psshar_dws);
DEFINE_RTYPE(psshl_hs);
DEFINE_RTYPE_RDP_RS1P(psshl_dhs);
DEFINE_RTYPE_RDP_RS1P(psshl_dws);
DEFINE_RTYPE(psshlr_hs);
DEFINE_RTYPE_RDP_RS1P(psshlr_dhs);
DEFINE_RTYPE_RDP_RS1P(psshlr_dws);
DEFINE_RTYPE(psh1add_h);
DEFINE_RTYPE_PAIR(psh1add_dh);
DEFINE_RTYPE_PAIR(psh1add_dw);
DEFINE_RTYPE(pssh1sadd_h);
DEFINE_RTYPE_PAIR(pssh1sadd_dh);
DEFINE_RTYPE_PAIR(pssh1sadd_dw);
// Type 2: rs1p - Narrowing with scalar rs2
DEFINE_RTYPE_RS1P(pnclip_bs);
DEFINE_RTYPE_RS1P(pnclip_hs);
DEFINE_RTYPE_RS1P(pnclipr_bs);
DEFINE_RTYPE_RS1P(pnclipr_hs);
DEFINE_RTYPE_RS1P(pnclipu_bs);
DEFINE_RTYPE_RS1P(pnclipu_hs);
DEFINE_RTYPE_RS1P(pnclipru_bs);
DEFINE_RTYPE_RS1P(pnclipru_hs);
DEFINE_RTYPE_RS1P(pnsra_bs);
DEFINE_RTYPE_RS1P(pnsra_hs);
DEFINE_RTYPE_RS1P(pnsrar_bs);
DEFINE_RTYPE_RS1P(pnsrar_hs);
DEFINE_RTYPE_RS1P(pnsrl_bs);
DEFINE_RTYPE_RS1P(pnsrl_hs);
// Type 1: rdp - Widening with scalar rs2
DEFINE_RTYPE_RDP(pwsll_bs);
DEFINE_RTYPE_RDP(pwsll_hs);
DEFINE_RTYPE_RDP(pwsla_bs);
DEFINE_RTYPE_RDP(pwsla_hs);
DEFINE_RTYPE(ppaire_b);
DEFINE_RTYPE(ppaire_h);
DEFINE_RTYPE_PAIR(ppaire_db);
DEFINE_RTYPE_PAIR(ppaire_dh);
DEFINE_RTYPE(ppaireo_b);
DEFINE_RTYPE(ppaireo_h);
DEFINE_RTYPE_PAIR(ppaireo_db);
DEFINE_RTYPE_PAIR(ppaireo_dh);
DEFINE_RTYPE(ppairo_b);
DEFINE_RTYPE(ppairo_h);
DEFINE_RTYPE_PAIR(ppairo_db);
DEFINE_RTYPE_PAIR(ppairo_dh);
DEFINE_RTYPE(ppairoe_b);
DEFINE_RTYPE(ppairoe_h);
DEFINE_RTYPE_PAIR(ppairoe_db);
DEFINE_RTYPE_PAIR(ppairoe_dh);
DEFINE_RTYPE(predsum_bs);
DEFINE_RTYPE(predsum_hs);
// Type 2: rs1p - Reduction sum (rd normal, rs1p is pair)
DEFINE_RTYPE_RS1P(predsum_dbs);
DEFINE_RTYPE_RS1P(predsum_dhs);
DEFINE_RTYPE(predsumu_bs);
DEFINE_RTYPE(predsumu_hs);
DEFINE_RTYPE_RS1P(predsumu_dbs);
DEFINE_RTYPE_RS1P(predsumu_dhs);
// Packed R1-type instructions (rd, rs1) - unary
DEFINE_R1TYPE(psabs_b);
DEFINE_R1TYPE(psabs_h);
// Type 3: rdp + rs1p - Doubleword unary ops
DEFINE_R1TYPE_RDP_RS1P(psabs_db);
DEFINE_R1TYPE_RDP_RS1P(psabs_dh);
DEFINE_R1TYPE(psext_h_b);
DEFINE_R1TYPE_RDP_RS1P(psext_dh_b);
DEFINE_R1TYPE_RDP_RS1P(psext_dw_b);
DEFINE_R1TYPE_RDP_RS1P(psext_dw_h);
// Packed I-type with shamt
DISASM_INSN("pslli.b", pslli_b, 0, {&xrd, &xrs1, &shamtb});
DISASM_INSN("pslli.h", pslli_h, 0, {&xrd, &xrs1, &shamth});
// Type 3: rdp + rs1p - Doubleword immediate shift
DISASM_INSN("pslli.db", pslli_db, 0, {&xrd_p, &xrs1_p, &shamtb});
DISASM_INSN("pslli.dh", pslli_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("pslli.dw", pslli_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
DISASM_INSN("psrai.b", psrai_b, 0, {&xrd, &xrs1, &shamtb});
DISASM_INSN("psrai.h", psrai_h, 0, {&xrd, &xrs1, &shamth});
DISASM_INSN("psrai.db", psrai_db, 0, {&xrd_p, &xrs1_p, &shamtb});
DISASM_INSN("psrai.dh", psrai_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("psrai.dw", psrai_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
DISASM_INSN("psrli.b", psrli_b, 0, {&xrd, &xrs1, &shamtb});
DISASM_INSN("psrli.h", psrli_h, 0, {&xrd, &xrs1, &shamth});
DISASM_INSN("psrli.db", psrli_db, 0, {&xrd_p, &xrs1_p, &shamtb});
DISASM_INSN("psrli.dh", psrli_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("psrli.dw", psrli_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
DISASM_INSN("psrari.h", psrari_h, 0, {&xrd, &xrs1, &shamth});
DISASM_INSN("psrari.dh", psrari_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("psrari.dw", psrari_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
DISASM_INSN("psati.h", psati_h, 0, {&xrd, &xrs1, &shamth});
DISASM_INSN("psati.dh", psati_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("psati.dw", psati_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
DISASM_INSN("pusati.h", pusati_h, 0, {&xrd, &xrs1, &shamth});
DISASM_INSN("pusati.dh", pusati_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("pusati.dw", pusati_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
DISASM_INSN("psslai.h", psslai_h, 0, {&xrd, &xrs1, &shamth});
DISASM_INSN("psslai.dh", psslai_dh, 0, {&xrd_p, &xrs1_p, &shamth});
DISASM_INSN("psslai.dw", psslai_dw, 0, {&xrd_p, &xrs1_p, &shamtw});
// Type 2: rs1p - Narrowing immediate (rd normal, rs1p is pair)
DISASM_INSN("pnclipi.b", pnclipi_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnclipi.h", pnclipi_h, 0, {&xrd, &xrs1_p, &shamtw});
DISASM_INSN("pnclipiu.b", pnclipiu_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnclipiu.h", pnclipiu_h, 0, {&xrd, &xrs1_p, &shamtw});
DISASM_INSN("pnclipri.b", pnclipri_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnclipri.h", pnclipri_h, 0, {&xrd, &xrs1_p, &shamtw});
DISASM_INSN("pnclipriu.b", pnclipriu_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnclipriu.h", pnclipriu_h, 0, {&xrd, &xrs1_p, &shamtw});
DISASM_INSN("pnsrai.b", pnsrai_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnsrai.h", pnsrai_h, 0, {&xrd, &xrs1_p, &shamtw});
DISASM_INSN("pnsrari.b", pnsrari_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnsrari.h", pnsrari_h, 0, {&xrd, &xrs1_p, &shamtw});
DISASM_INSN("pnsrli.b", pnsrli_b, 0, {&xrd, &xrs1_p, &shamth});
DISASM_INSN("pnsrli.h", pnsrli_h, 0, {&xrd, &xrs1_p, &shamtw});
// Type 1: rdp - Widening immediate (rdp is pair, rs1 normal)
DISASM_INSN("pwslli.b", pwslli_b, 0, {&xrd_p, &xrs1, &shamtb});
DISASM_INSN("pwslli.h", pwslli_h, 0, {&xrd_p, &xrs1, &shamth});
DISASM_INSN("pwslai.b", pwslai_b, 0, {&xrd_p, &xrs1, &shamtb});
DISASM_INSN("pwslai.h", pwslai_h, 0, {&xrd_p, &xrs1, &shamth});
// Packed load-immediate instructions (rd, imm) - Type 1: rdp for _db, _dh
DISASM_INSN("pli.b", pli_b, 0, {&xrd, &p_imm8});
DISASM_INSN("pli.h", pli_h, 0, {&xrd, &p_imm10csl});
DISASM_INSN("pli.db", pli_db, 0, {&xrd_p, &p_imm8});
DISASM_INSN("pli.dh", pli_dh, 0, {&xrd_p, &p_imm10csl});
DISASM_INSN("plui.h", plui_h, 0, {&xrd, &p_imm10csr});
DISASM_INSN("plui.dh", plui_dh, 0, {&xrd_p, &p_imm10csr});
// Packed multiply/mac instructions
DEFINE_RTYPE(pmul_h_b00);
DEFINE_RTYPE(pmul_h_b01);
DEFINE_RTYPE(pmul_h_b11);
DEFINE_RTYPE(pmulu_h_b00);
DEFINE_RTYPE(pmulu_h_b01);
DEFINE_RTYPE(pmulu_h_b11);
DEFINE_RTYPE(pmulsu_h_b00);
DEFINE_RTYPE(pmulsu_h_b11);
DEFINE_RTYPE(pmulh_h);
DEFINE_RTYPE(pmulhu_h);
DEFINE_RTYPE(pmulhsu_h);
DEFINE_RTYPE(pmulh_h_b0);
DEFINE_RTYPE(pmulh_h_b1);
DEFINE_RTYPE(pmulhsu_h_b0);
DEFINE_RTYPE(pmulhsu_h_b1);
DEFINE_RTYPE(pmulhr_h);
DEFINE_RTYPE(pmulhru_h);
DEFINE_RTYPE(pmulhrsu_h);
DEFINE_RTYPE(pmulq_h);
DEFINE_RTYPE(pmulqr_h);
DEFINE_RTYPE(pmhacc_h);
DEFINE_RTYPE(pmhaccu_h);
DEFINE_RTYPE(pmhaccsu_h);
DEFINE_RTYPE(pmhacc_h_b0);
DEFINE_RTYPE(pmhacc_h_b1);
DEFINE_RTYPE(pmhaccsu_h_b0);
DEFINE_RTYPE(pmhaccsu_h_b1);
DEFINE_RTYPE(pmhracc_h);
DEFINE_RTYPE(pmhraccu_h);
DEFINE_RTYPE(pmhraccsu_h);
DEFINE_RTYPE(pmq2add_h);
DEFINE_RTYPE(pmq2adda_h);
DEFINE_RTYPE(pmqr2add_h);
DEFINE_RTYPE(pmqr2adda_h);
// Packed widening instructions - Type 1: rdp (pair result, normal sources)
DEFINE_RTYPE_RDP(pwadd_b);
DEFINE_RTYPE_RDP(pwadd_h);
DEFINE_RTYPE_RDP(pwaddu_b);
DEFINE_RTYPE_RDP(pwaddu_h);
DEFINE_RTYPE_RDP(pwadda_b);
DEFINE_RTYPE_RDP(pwadda_h);
DEFINE_RTYPE_RDP(pwaddau_b);
DEFINE_RTYPE_RDP(pwaddau_h);
DEFINE_RTYPE_RDP(pwsub_b);
DEFINE_RTYPE_RDP(pwsub_h);
DEFINE_RTYPE_RDP(pwsubu_b);
DEFINE_RTYPE_RDP(pwsubu_h);
DEFINE_RTYPE_RDP(pwsuba_b);
DEFINE_RTYPE_RDP(pwsuba_h);
DEFINE_RTYPE_RDP(pwsubau_b);
DEFINE_RTYPE_RDP(pwsubau_h);
DEFINE_RTYPE_RDP(pwmul_b);
DEFINE_RTYPE_RDP(pwmul_h);
DEFINE_RTYPE_RDP(pwmulu_b);
DEFINE_RTYPE_RDP(pwmulu_h);
DEFINE_RTYPE_RDP(pwmulsu_b);
DEFINE_RTYPE_RDP(pwmulsu_h);
DEFINE_RTYPE_RDP(pwmacc_h);
DEFINE_RTYPE_RDP(pwmaccu_h);
DEFINE_RTYPE_RDP(pwmaccsu_h);
// Packed multi-add instructions
DEFINE_RTYPE(pm2add_h);
DEFINE_RTYPE(pm2add_hx);
DEFINE_RTYPE(pm2addu_h);
DEFINE_RTYPE(pm2addsu_h);
DEFINE_RTYPE(pm2adda_h);
DEFINE_RTYPE(pm2adda_hx);
DEFINE_RTYPE(pm2addau_h);
DEFINE_RTYPE(pm2addasu_h);
DEFINE_RTYPE(pm2sub_h);
DEFINE_RTYPE(pm2sub_hx);
DEFINE_RTYPE(pm2suba_h);
DEFINE_RTYPE(pm2suba_hx);
DEFINE_RTYPE(pm2sadd_h);
DEFINE_RTYPE(pm2sadd_hx);
// pm2wadd produces widened result - Type 1: rdp
DEFINE_RTYPE_RDP(pm2wadd_h);
DEFINE_RTYPE_RDP(pm2wadd_hx);
DEFINE_RTYPE_RDP(pm2waddu_h);
DEFINE_RTYPE_RDP(pm2waddsu_h);
DEFINE_RTYPE_RDP(pm2wadda_h);
DEFINE_RTYPE_RDP(pm2wadda_hx);
DEFINE_RTYPE_RDP(pm2waddau_h);
DEFINE_RTYPE_RDP(pm2waddasu_h);
DEFINE_RTYPE_RDP(pm2wsub_h);
DEFINE_RTYPE_RDP(pm2wsub_hx);
DEFINE_RTYPE_RDP(pm2wsuba_h);
DEFINE_RTYPE_RDP(pm2wsuba_hx);
DEFINE_RTYPE(pm4add_b);
DEFINE_RTYPE(pm4addu_b);
DEFINE_RTYPE(pm4addsu_b);
DEFINE_RTYPE(pm4adda_b);
DEFINE_RTYPE(pm4addau_b);
DEFINE_RTYPE(pm4addasu_b);
// Zip/Unzip instructions
DEFINE_R1TYPE(zip8p);
DEFINE_R1TYPE(zip8hp);
DEFINE_R1TYPE(unzip8p);
DEFINE_R1TYPE(unzip8hp);
DEFINE_R1TYPE(unzip16p);
DEFINE_R1TYPE(unzip16hp);
// Type 1: rdp - Widening zip (pair result)
DEFINE_R1TYPE_RDP(wzip8p);
DEFINE_R1TYPE_RDP(wzip16p);
// mqwacc instructions - Type 1: rdp (widened 64-bit result)
DEFINE_RTYPE_RDP(mqwacc);
DEFINE_RTYPE_RDP(mqrwacc);
DEFINE_RTYPE_RDP(pmqwacc_h);
DEFINE_RTYPE_RDP(pmqrwacc_h);
// RV64 P-extension instructions (word-sized operations)
// These share opcodes with RV32 scalar instructions
if (xlen_eq(64)) {
// R1-type unary instructions
DEFINE_R1TYPE(absw);
DEFINE_R1TYPE(clsw);
// R-type scalar MAC/MUL instructions (word-sized)
DEFINE_RTYPE(macc_w00);
DEFINE_RTYPE(macc_w01);
DEFINE_RTYPE(macc_w11);
DEFINE_RTYPE(maccu_w00);
DEFINE_RTYPE(maccu_w01);
DEFINE_RTYPE(maccu_w11);
DEFINE_RTYPE(maccsu_w00);
DEFINE_RTYPE(maccsu_w11);
DEFINE_RTYPE(mul_w00);
DEFINE_RTYPE(mul_w01);
DEFINE_RTYPE(mul_w11);
DEFINE_RTYPE(mulu_w00);
DEFINE_RTYPE(mulu_w01);
DEFINE_RTYPE(mulu_w11);
DEFINE_RTYPE(mulsu_w00);
DEFINE_RTYPE(mulsu_w11);
DEFINE_RTYPE(mqacc_w00);
DEFINE_RTYPE(mqacc_w01);
DEFINE_RTYPE(mqacc_w11);
DEFINE_RTYPE(mqracc_w00);
DEFINE_RTYPE(mqracc_w01);
DEFINE_RTYPE(mqracc_w11);
// R-type packed word-sized instructions (share opcode with RV32 scalar)
DEFINE_RTYPE(paadd_w);
DEFINE_RTYPE(paaddu_w);
DEFINE_RTYPE(paas_wx);
DEFINE_RTYPE(padd_w);
DEFINE_RTYPE(padd_ws);
DEFINE_RTYPE(pasa_wx);
DEFINE_RTYPE(pasub_w);
DEFINE_RTYPE(pasubu_w);
DEFINE_RTYPE(pas_wx);
DEFINE_RTYPE(pmax_w);
DEFINE_RTYPE(pmaxu_w);
DEFINE_RTYPE(pmin_w);
DEFINE_RTYPE(pminu_w);
DEFINE_RTYPE(pmseq_w);
DEFINE_RTYPE(pmslt_w);
DEFINE_RTYPE(pmsltu_w);
DEFINE_RTYPE(psadd_w);
DEFINE_RTYPE(psaddu_w);
DEFINE_RTYPE(psa_wx);
DEFINE_RTYPE(psas_wx);
DEFINE_RTYPE(pssa_wx);
DEFINE_RTYPE(pssub_w);
DEFINE_RTYPE(pssubu_w);
DEFINE_RTYPE(psub_w);
DEFINE_RTYPE(psh1add_w);
DEFINE_RTYPE(pssh1sadd_w);
DEFINE_RTYPE(psll_ws);
DEFINE_RTYPE(psra_ws);
DEFINE_RTYPE(psrl_ws);
DEFINE_RTYPE(pssha_ws);
DEFINE_RTYPE(psshar_ws);
DEFINE_RTYPE(psshl_ws);
DEFINE_RTYPE(psshlr_ws);
DEFINE_RTYPE(shl);
DEFINE_RTYPE(shlr);
DEFINE_RTYPE(pnclipp_b);
DEFINE_RTYPE(pnclipp_h);
DEFINE_RTYPE(pnclipp_w);
DEFINE_RTYPE(pnclipup_b);
DEFINE_RTYPE(pnclipup_h);
DEFINE_RTYPE(pnclipup_w);
DEFINE_RTYPE(ppaireo_w);
DEFINE_RTYPE(ppairoe_w);
DEFINE_RTYPE(ppairo_w);
DEFINE_RTYPE(predsum_ws);
DEFINE_RTYPE(predsumu_ws);
// Packed multiply/mac word-sized instructions (share opcode with RV32 scalar)
DEFINE_RTYPE(pmul_w_h00);
DEFINE_RTYPE(pmul_w_h01);
DEFINE_RTYPE(pmul_w_h11);
DEFINE_RTYPE(pmulu_w_h00);
DEFINE_RTYPE(pmulu_w_h01);
DEFINE_RTYPE(pmulu_w_h11);
DEFINE_RTYPE(pmulsu_w_h00);
DEFINE_RTYPE(pmulsu_w_h11);
DEFINE_RTYPE(pmulh_w);
DEFINE_RTYPE(pmulhu_w);
DEFINE_RTYPE(pmulhsu_w);
DEFINE_RTYPE(pmulh_w_h0);
DEFINE_RTYPE(pmulh_w_h1);
DEFINE_RTYPE(pmulhsu_w_h0);
DEFINE_RTYPE(pmulhsu_w_h1);
DEFINE_RTYPE(pmulhr_w);
DEFINE_RTYPE(pmulhru_w);
DEFINE_RTYPE(pmulhrsu_w);
DEFINE_RTYPE(pmulq_w);
DEFINE_RTYPE(pmulqr_w);
DEFINE_RTYPE(pmacc_w_h00);
DEFINE_RTYPE(pmacc_w_h01);
DEFINE_RTYPE(pmacc_w_h11);
DEFINE_RTYPE(pmaccu_w_h00);
DEFINE_RTYPE(pmaccu_w_h01);
DEFINE_RTYPE(pmaccu_w_h11);
DEFINE_RTYPE(pmaccsu_w_h00);
DEFINE_RTYPE(pmaccsu_w_h11);
DEFINE_RTYPE(pmhacc_w);
DEFINE_RTYPE(pmhaccu_w);
DEFINE_RTYPE(pmhaccsu_w);
DEFINE_RTYPE(pmhacc_w_h0);
DEFINE_RTYPE(pmhacc_w_h1);
DEFINE_RTYPE(pmhaccsu_w_h0);
DEFINE_RTYPE(pmhaccsu_w_h1);
DEFINE_RTYPE(pmhracc_w);
DEFINE_RTYPE(pmhraccu_w);
DEFINE_RTYPE(pmhraccsu_w);
DEFINE_RTYPE(pmqacc_w_h00);
DEFINE_RTYPE(pmqacc_w_h01);
DEFINE_RTYPE(pmqacc_w_h11);
DEFINE_RTYPE(pmqracc_w_h00);
DEFINE_RTYPE(pmqracc_w_h01);
DEFINE_RTYPE(pmqracc_w_h11);
DEFINE_RTYPE(pmq2add_w);
DEFINE_RTYPE(pmq2adda_w);
DEFINE_RTYPE(pmqr2add_w);
DEFINE_RTYPE(pmqr2adda_w);
// Packed multi-add word-sized instructions
DEFINE_RTYPE(pm2add_w);
DEFINE_RTYPE(pm2add_wx);
DEFINE_RTYPE(pm2addu_w);
DEFINE_RTYPE(pm2addsu_w);
DEFINE_RTYPE(pm2adda_w);
DEFINE_RTYPE(pm2adda_wx);
DEFINE_RTYPE(pm2addau_w);
DEFINE_RTYPE(pm2addasu_w);
DEFINE_RTYPE(pm2sub_w);
DEFINE_RTYPE(pm2sub_wx);
DEFINE_RTYPE(pm2suba_w);
DEFINE_RTYPE(pm2suba_wx);
DEFINE_RTYPE(pm4add_h);
DEFINE_RTYPE(pm4addu_h);
DEFINE_RTYPE(pm4addsu_h);
DEFINE_RTYPE(pm4adda_h);
DEFINE_RTYPE(pm4addau_h);
DEFINE_RTYPE(pm4addasu_h);
// R1-type packed word-sized unary instructions
DEFINE_R1TYPE(psext_w_b);
DEFINE_R1TYPE(psext_w_h);
DEFINE_R1TYPE(zip16p);
DEFINE_R1TYPE(zip16hp);
// Packed I-type with shamt (word-sized) - share opcode with RV32 scalar
DISASM_INSN("pslli.w", pslli_w, 0, {&xrd, &xrs1, &shamtw});
DISASM_INSN("psrai.w", psrai_w, 0, {&xrd, &xrs1, &shamtw});
DISASM_INSN("psrli.w", psrli_w, 0, {&xrd, &xrs1, &shamtw});
DISASM_INSN("psrari.w", psrari_w, 0, {&xrd, &xrs1, &shamtw});
DISASM_INSN("psati.w", psati_w, 0, {&xrd, &xrs1, &shamtw});
DISASM_INSN("pusati.w", pusati_w, 0, {&xrd, &xrs1, &shamtw});
DISASM_INSN("psslai.w", psslai_w, 0, {&xrd, &xrs1, &shamtw});
// Packed load-immediate word-sized instructions
DISASM_INSN("pli.w", pli_w, 0, {&xrd, &p_imm10csl});
DISASM_INSN("plui.w", plui_w, 0, {&xrd, &p_imm10csr});
}
}
}
disassembler_t::disassembler_t(const isa_parser_t *isa, bool strict)

16
riscv/decode.h
View File

@ -98,6 +98,9 @@ public:
uint64_t iorw() { return x(20, 8); }
uint64_t bs() { return x(30, 2); } // Crypto ISE - SM4/AES32 byte select.
uint64_t rcon() { return x(20, 4); } // Crypto ISE - AES64 round const.
uint64_t rd_p() { return x(8, 4) * 2; }
uint64_t rs1_p() { return x(16, 4) * 2; }
uint64_t rs2_p() { return x(21, 4) * 2; }
[[maybe_unused]] int64_t rvc_opcode() { return x(0, 2); }
int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
@ -148,11 +151,14 @@ public:
uint64_t v_mew() { return x(28, 1); }
uint64_t v_zimm6() { return x(15, 5) + (x(26, 1) << 5); }
uint64_t p_imm2() { return x(20, 2); }
uint64_t p_imm3() { return x(20, 3); }
uint64_t p_imm4() { return x(20, 4); }
uint64_t p_imm5() { return x(20, 5); }
uint64_t p_imm6() { return x(20, 6); }
uint64_t p_imm8() { return x(16, 8); }
uint64_t p_imm10csl() { return x(16, 9) + (x(15, 1) << 9); }
uint64_t p_imm10csr() { return (x(24, 1) << 6) + (x(15, 9) << 7); }
uint64_t p_imm10csrw() { return (x(24, 1) << 22) + (x(15, 9) << 23); }
uint64_t shamtd() { return x(20, 6); }
uint64_t shamtw() { return x(20, 5); }
uint64_t shamth() { return x(20, 4); }
uint64_t shamtb() { return x(20, 3); }
uint64_t b_imm5() { return (x(20, 5) == 0) ? -1ul : x(20, 5); }

19
riscv/decode_macros.h
View File

@ -52,6 +52,23 @@
WRITE_REG((reg) + 1, (sreg_t(val)) >> 32); \
}
// RVP macros
#define WRITE_P_REG_PAIR(reg, value) \
if(reg != 0) { \
uint64_t val = (value); \
WRITE_REG(reg, sext32(val)); \
WRITE_REG((reg) + 1, (sreg_t(val)) >> 32); \
}
#define P_READ_REG_PAIR(reg) ({ \
(reg) == 0 ? reg_t(0) : \
(READ_REG((reg) + 1) << 32) + zext32(READ_REG(reg)); })
#define P_RS1_PAIR P_READ_REG_PAIR(insn.rs1_p())
#define P_RS2_PAIR P_READ_REG_PAIR(insn.rs2_p())
#define P_RD_PAIR P_READ_REG_PAIR(insn.rd_p())
#define WRITE_P_RD_PAIR(value) WRITE_P_REG_PAIR(insn.rd_p(), value)
// RVC macros
#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
@ -219,6 +236,8 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
#define zext(x, pos) (((reg_t)(x) << (64 - (pos))) >> (64 - (pos)))
#define sext_xlen(x) sext(x, xlen)
#define zext_xlen(x) zext(x, xlen)
#define sext_xlen_pair(x) (xlen == 32 ? sext(x, 64) : (sreg_t)(x))
#define zext_xlen_pair(x) (xlen == 32 ? zext(x, 64) : (reg_t)(x))
#define set_pc(x) \
do { if (unlikely((x) & ~p->pc_alignment_mask())) \

1836
riscv/encoding.h
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File diff suppressed because it is too large

1
riscv/insn_template.h
View File

@ -7,6 +7,7 @@
#include "internals.h"
#include "specialize.h"
#include "tracer.h"
#include "p_ext_macros.h"
#include "v_ext_macros.h"
#include "debug_defines.h"
#include <assert.h>

3
riscv/insns/aadd.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((RS1 + RS2)>>1);

3
riscv/insns/aaddu.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((0ULL + (uint32_t)RS1 + (uint32_t)RS2)>>1);

4
riscv/insns/abs.h
View File

@ -0,0 +1,4 @@
require_extension('P');
reg_t s1 = RS1;
reg_t result = (int64_t(s1) < 0) ? -s1 : s1;
WRITE_RD(sext_xlen(result));

5
riscv/insns/absw.h
View File

@ -0,0 +1,5 @@
require_rv64;
require_extension('P');
reg_t s1_w = sext32(RS1);
reg_t result = (int32_t(s1_w) < 0) ? -s1_w : s1_w;
WRITE_RD(sext_xlen(result));

3
riscv/insns/addd.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_P_RD_PAIR(P_RS1_PAIR + P_RS2_PAIR);

3
riscv/insns/asub.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((RS1 - RS2)>>1);

3
riscv/insns/asubu.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((0ULL + (uint32_t)RS1 - (uint32_t)RS2)>>1);

10
riscv/insns/cls.h
View File

@ -0,0 +1,10 @@
require_extension('P');
reg_t x = xlen - 1;
reg_t msb = (RS1 >> (xlen - 1)) & 1;
for (int i = 0; i < xlen - 1; i++) {
if (msb != ((RS1 >> (xlen - i - 2)) & 1)) {
x = i;
break;
}
}
WRITE_RD(sext_xlen(x));

11
riscv/insns/clsw.h
View File

@ -0,0 +1,11 @@
require_rv64;
require_extension('P');
reg_t x = 32 - 1;
reg_t msb = (RS1 >> (32 - 1)) & 1;
for (int i = 0; i < 32 - 1; i++) {
if (msb != ((RS1 >> (32 - i - 2)) & 1)) {
x = i;
break;
}
}
WRITE_RD(sext_xlen(x));

3
riscv/insns/macc_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + sext(RS1, 16) * sext(RS2, 16));

3
riscv/insns/macc_h01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + sext(RS1, 16) * sext(RS2 >> 16, 16));

3
riscv/insns/macc_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + sext(RS1 >> 16, 16) * sext(RS2 >> 16, 16));

3
riscv/insns/macc_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + sext32(RS1) * sext32(RS2));

3
riscv/insns/macc_w01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + sext32(RS1) * sext32(RS2 >> 32));

3
riscv/insns/macc_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + sext32(RS1 >> 32) * sext32(RS2 >> 32));

3
riscv/insns/maccsu_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + sext(RS1, 16) * zext(RS2, 16));

3
riscv/insns/maccsu_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + sext(RS1 >> 16, 16) * zext(RS2 >> 16, 16));

3
riscv/insns/maccsu_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + sext32(RS1) * zext32(RS2));

3
riscv/insns/maccsu_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + sext32(RS1 >> 32) * zext32(RS2 >> 32));

3
riscv/insns/maccu_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + zext(RS1, 16) * zext(RS2, 16));

3
riscv/insns/maccu_h01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + zext(RS1, 16) * zext(RS2 >> 16, 16));

3
riscv/insns/maccu_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + zext(RS1 >> 16, 16) * zext(RS2 >> 16, 16));

3
riscv/insns/maccu_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + zext32(RS1) * zext32(RS2));

3
riscv/insns/maccu_w01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + zext32(RS1) * zext32(RS2 >> 32));

3
riscv/insns/maccu_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + zext32(RS1 >> 32) * zext32(RS2 >> 32));

2
riscv/insns/merge.h
View File

@ -0,0 +1,2 @@
require_extension('P');
WRITE_RD((RS2 & RD) | (RS1 & ~RD));

4
riscv/insns/mhacc.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * sext32(RS2);
WRITE_RD(RD + (mres >> 32));

4
riscv/insns/mhacc_h0.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * sext32(P_FIELD(RS2, 0, 16));
WRITE_RD(RD + (mres >> 32));

4
riscv/insns/mhacc_h1.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * sext32(P_FIELD(RS2, 1, 16));
WRITE_RD(RD + (mres >> 32));

4
riscv/insns/mhaccsu.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * reg_t((uint32_t)RS2);
WRITE_RD(RD + (mres >> 32));

4
riscv/insns/mhaccsu_h0.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * (uint32_t)P_FIELD(RS2, 0, 16);
WRITE_RD(RD + (mres >> 32));

4
riscv/insns/mhaccsu_h1.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * (uint32_t)P_FIELD(RS2, 1, 16);
WRITE_RD(RD + (mres >> 32));

4
riscv/insns/mhaccu.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
uint64_t mres = reg_t((uint32_t)RS1) * reg_t((uint32_t)RS2);
WRITE_RD(RD + (mres >> 32));

5
riscv/insns/mhracc.h
View File

@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * sext32(RS2);
int32_t round = ((mres >> 31) + 1) >> 1;
WRITE_RD(RD + round);

5
riscv/insns/mhraccsu.h
View File

@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
sreg_t mres = sext(RS1,64) * reg_t((uint32_t)RS2);
int32_t round = ((mres >> 31) + 1) >> 1;
WRITE_RD(RD + round);

5
riscv/insns/mhraccu.h
View File

@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
reg_t mres = reg_t((uint32_t)RS1) * reg_t((uint32_t)RS2);
uint32_t round = ((mres >> 31) + 1) >> 1;
WRITE_RD(RD + round);

3
riscv/insns/mqacc_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + (((int32_t)P_FIELD(RS1, 0, 16) * P_FIELD(RS2, 0, 16)) >> 15));

3
riscv/insns/mqacc_h01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + (((int32_t)P_FIELD(RS1, 0, 16) * P_FIELD(RS2, 1, 16)) >> 15));

3
riscv/insns/mqacc_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + (((int32_t)P_FIELD(RS1, 1, 16) * P_FIELD(RS2, 1, 16)) >> 15));

3
riscv/insns/mqacc_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + (((sreg_t)P_FIELD(RS1, 0, 32) * P_FIELD(RS2, 0, 32)) >> 31));

3
riscv/insns/mqacc_w01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + (((sreg_t)P_FIELD(RS1, 0, 32) * P_FIELD(RS2, 1, 32)) >> 31));

3
riscv/insns/mqacc_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + (((sreg_t)P_FIELD(RS1, 1, 32) * P_FIELD(RS2, 1, 32)) >> 31));

3
riscv/insns/mqracc_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + (((int32_t)P_FIELD(RS1, 0, 16) * P_FIELD(RS2, 0, 16) + 0x4000) >> 15));

3
riscv/insns/mqracc_h01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + (((int32_t)P_FIELD(RS1, 0, 16) * P_FIELD(RS2, 1, 16) + 0x4000) >> 15));

3
riscv/insns/mqracc_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RD + (((int32_t)P_FIELD(RS1, 1, 16) * P_FIELD(RS2, 1, 16) + 0x4000) >> 15));

3
riscv/insns/mqracc_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + (((sreg_t)P_FIELD(RS1, 0, 32) * P_FIELD(RS2, 0, 32) + 0x40000000) >> 31));

3
riscv/insns/mqracc_w01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + (((sreg_t)P_FIELD(RS1, 0, 32) * P_FIELD(RS2, 1, 32) + 0x40000000) >> 31));

3
riscv/insns/mqracc_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(RD + (((sreg_t)P_FIELD(RS1, 1, 32) * P_FIELD(RS2, 1, 32) + 0x40000000) >> 31));

3
riscv/insns/mqrwacc.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_P_RD_PAIR(P_RD_PAIR + (((sreg_t)RS1*(sreg_t)RS2 + 0x40000000) >> 31));

3
riscv/insns/mqwacc.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_P_RD_PAIR(P_RD_PAIR + (((sreg_t)RS1*(sreg_t)RS2) >> 31));

3
riscv/insns/mseq.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(RS1 == RS2 ? -1 : 0);

3
riscv/insns/mslt.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((int32_t)RS1 < (int32_t)RS2 ? -1 : 0);

3
riscv/insns/msltu.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((uint32_t)RS1 < (uint32_t)RS2 ? -1 : 0);

3
riscv/insns/mul_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(sext(RS1, 16) * sext(RS2, 16));

3
riscv/insns/mul_h01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(sext(RS1, 16) * sext(RS2 >> 16, 16));

3
riscv/insns/mul_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(sext(RS1 >> 16, 16) * sext(RS2 >> 16, 16));

3
riscv/insns/mul_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(sext32(RS1) * sext32(RS2));

3
riscv/insns/mul_w01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(sext32(RS1) * sext32(RS2 >> 32));

3
riscv/insns/mul_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(sext32(RS1 >> 32) * sext32(RS2 >> 32));

4
riscv/insns/mulh_h0.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
int64_t mres = sext(RS1,64) * sext(P_FIELD(RS2, 0, 16),64);
WRITE_RD(mres>>32);

4
riscv/insns/mulh_h1.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
int64_t mres = sext(RS1,64) * sext(P_FIELD(RS2, 1, 16),64);
WRITE_RD(mres>>32);

4
riscv/insns/mulhr.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
int64_t mres = sext(RS1,64) * sext(RS2,64);
WRITE_RD(((mres >> 31) + 1) >> 1);

4
riscv/insns/mulhrsu.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext(RS1,64) * reg_t((uint32_t)RS2);
WRITE_RD(((mres >> 31) + 1) >> 1);

4
riscv/insns/mulhru.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = reg_t((uint32_t)RS1) * reg_t((uint32_t)RS2);
WRITE_RD(((mres >> 31) + 1) >> 1);

4
riscv/insns/mulhsu_h0.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * (uint32_t)P_FIELD(RS2, 0, 16);
WRITE_RD(mres >> 32);

4
riscv/insns/mulhsu_h1.h
View File

@ -0,0 +1,4 @@
require_extension('P');
require_rv32;
sreg_t mres = sext32(RS1) * (uint32_t)P_FIELD(RS2, 1, 16);
WRITE_RD(mres >> 32);

8
riscv/insns/mulq.h
View File

@ -0,0 +1,8 @@
require_extension('P');
require_rv32;
if ((RS1 != (reg_t)INT32_MIN) || (RS2 != (reg_t)INT32_MIN)) {
WRITE_RD((RS1 * RS2) >> 31);
} else {
WRITE_RD(INT32_MAX);
P.VU.vxsat->write(1);
}

8
riscv/insns/mulqr.h
View File

@ -0,0 +1,8 @@
require_extension('P');
require_rv32;
if ((RS1 != (reg_t)INT32_MIN) || (RS2 != (reg_t)INT32_MIN)) {
WRITE_RD((((RS1 * RS2) >> 30) + 1) >> 1);
} else {
WRITE_RD(INT32_MAX);
P.VU.vxsat->write(1);
}

3
riscv/insns/mulsu_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(sext(RS1, 16) * zext(RS2, 16));

3
riscv/insns/mulsu_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(sext(RS1 >> 16, 16) * zext(RS2 >> 16, 16));

3
riscv/insns/mulsu_w00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(sext32(RS1) * zext32(RS2));

3
riscv/insns/mulsu_w11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(sext32(RS1 >> 32) * zext32(RS2 >> 32));

3
riscv/insns/mulu_h00.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(zext(RS1, 16) * zext(RS2, 16));

3
riscv/insns/mulu_h01.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(zext(RS1, 16) * zext(RS2 >> 16, 16));

3
riscv/insns/mulu_h11.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(zext(RS1 >> 16, 16) * zext(RS2 >> 16, 16));

3
riscv/insns/mulu_w00.h
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@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(zext32(RS1) * zext32(RS2));

3
riscv/insns/mulu_w01.h
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@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(zext32(RS1) * zext32(RS2 >> 32));

3
riscv/insns/mulu_w11.h
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@ -0,0 +1,3 @@
require_extension('P');
require_rv64;
WRITE_RD(zext32(RS1 >> 32) * zext32(RS2 >> 32));

2
riscv/insns/mvm.h
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@ -0,0 +1,2 @@
require_extension('P');
WRITE_RD((RS1 & RS2) | (RD & ~RS2));

2
riscv/insns/mvmn.h
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@ -0,0 +1,2 @@
require_extension('P');
WRITE_RD((RD & RS2) | (RS1 & ~RS2));

5
riscv/insns/nclip.h
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@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
sreg_t tmp = (sreg_t)P_RS1_PAIR >> (RS2 & 0x3f);
int32_t result = P_SAT(32, tmp);
WRITE_RD(result);

5
riscv/insns/nclipi.h
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@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
sreg_t tmp = (sreg_t)P_RS1_PAIR >> insn.shamtd();
int32_t result = P_SAT(32, tmp);
WRITE_RD(result);

5
riscv/insns/nclipiu.h
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@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
reg_t tmp = (reg_t)P_RS1_PAIR >> insn.shamtd();
uint32_t result = P_USAT_FULL(32, (sreg_t)tmp);
WRITE_RD(result);

11
riscv/insns/nclipr.h
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@ -0,0 +1,11 @@
require_extension('P');
require_rv32;
sreg_t val = (sreg_t)P_RS1_PAIR;
uint32_t shamt = RS2 & 0x3f;
sreg_t result;
if (shamt == 0) {
result = P_SAT(32, val);
} else {
result = P_SAT(32, (val >> shamt) + ((val >> (shamt - 1)) & 1));
}
WRITE_RD(result);

11
riscv/insns/nclipri.h
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@ -0,0 +1,11 @@
require_extension('P');
require_rv32;
sreg_t val = (sreg_t)P_RS1_PAIR;
uint32_t shamt = insn.shamtd();
sreg_t result;
if (shamt == 0) {
result = P_SAT(32, val);
} else {
result = P_SAT(32, (val >> shamt) + ((val >> (shamt - 1)) & 1));
}
WRITE_RD(result);

11
riscv/insns/nclipriu.h
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@ -0,0 +1,11 @@
require_extension('P');
require_rv32;
reg_t val = (reg_t)P_RS1_PAIR;
uint32_t shamt = insn.shamtd();
reg_t result;
if (shamt == 0) {
result = P_USAT_FULL(32, (sreg_t)val);
} else {
result = P_USAT_FULL(32, (sreg_t)((val >> shamt) + ((val >> (shamt - 1)) & 1)));
}
WRITE_RD(result);

11
riscv/insns/nclipru.h
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@ -0,0 +1,11 @@
require_extension('P');
require_rv32;
reg_t val = (reg_t)P_RS1_PAIR;
uint32_t shamt = RS2 & 0x3f;
reg_t result;
if (shamt == 0) {
result = P_USAT_FULL(32, (sreg_t)val);
} else {
result = P_USAT_FULL(32, (sreg_t)((val >> shamt) + ((val >> (shamt - 1)) & 1)));
}
WRITE_RD(result);

5
riscv/insns/nclipu.h
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@ -0,0 +1,5 @@
require_extension('P');
require_rv32;
reg_t tmp = (reg_t)P_RS1_PAIR >> (RS2 & 0x3f);
uint32_t result = P_USAT_FULL(32, (sreg_t)tmp);
WRITE_RD(result);

3
riscv/insns/nsra.h
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@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((sreg_t)P_RS1_PAIR >> (RS2 & 0x3f));

3
riscv/insns/nsrai.h
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@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD((sreg_t)P_RS1_PAIR >> insn.shamtd());

11
riscv/insns/nsrar.h
View File

@ -0,0 +1,11 @@
require_extension('P');
require_rv32;
sreg_t val = (sreg_t)P_RS1_PAIR;
uint32_t shamt = RS2 & 0x3f;
sreg_t result;
if (shamt == 0) {
result = val;
} else {
result = (val >> shamt) + ((val >> (shamt - 1)) & 1);
}
WRITE_RD(result);

11
riscv/insns/nsrari.h
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@ -0,0 +1,11 @@
require_extension('P');
require_rv32;
sreg_t val = (sreg_t)P_RS1_PAIR;
uint32_t shamt = insn.shamtd();
sreg_t result;
if (shamt == 0) {
result = val;
} else {
result = (val >> shamt) + ((val >> (shamt - 1)) & 1);
}
WRITE_RD(result);

3
riscv/insns/nsrl.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(P_RS1_PAIR >> (RS2 & 0x3f));

3
riscv/insns/nsrli.h
View File

@ -0,0 +1,3 @@
require_extension('P');
require_rv32;
WRITE_RD(P_RS1_PAIR >> insn.shamtd());

3
riscv/insns/paadd_b.h
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@ -0,0 +1,3 @@
P_RD_RS1_RS2_LOOP(8,8,8, {
p_rd = (p_rs1 + p_rs2) >> 1;
})

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