rvv: add reg checking rule for comparison instrucitons

include:
    1. integer comparison
    2. float comparison

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/decode.h

@@ -386,6 +386,15 @@ static inline bool is_overlapped(const int astart, const int asize,
 
 #define VI_CHECK_SS \
   require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul));
+#define VI_CHECK_MSS(is_vs1) \
+  if (P.VU.vlmul > 1) { \
+    require(!is_overlapped(insn.rd(), 1, insn.rs2(), P.VU.vlmul)); \
+    require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
+    if (is_vs1) {\
+      require(!is_overlapped(insn.rd(), 1, insn.rs1(), P.VU.vlmul)); \
+      require((insn.rs1() & (P.VU.vlmul - 1)) == 0); \
+    } \
+  }
 
 #define VI_CHECK_SD \
   require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul * 2));
@@ -604,6 +613,7 @@ static inline bool is_overlapped(const int astart, const int asize,
 
 // comparision result to masking register
 #define VI_VV_LOOP_CMP(BODY) \
+  VI_CHECK_MSS(true); \
   VI_LOOP_CMP_BASE \
   if (sew == e8){ \
     VV_PARAMS(e8); \
@@ -621,6 +631,7 @@ static inline bool is_overlapped(const int astart, const int asize,
   VI_LOOP_CMP_END
 
 #define VI_VX_LOOP_CMP(BODY) \
+  VI_CHECK_MSS(false); \
   VI_LOOP_CMP_BASE \
   if (sew == e8){ \
     VX_PARAMS(e8); \
@@ -638,6 +649,7 @@ static inline bool is_overlapped(const int astart, const int asize,
   VI_LOOP_CMP_END
 
 #define VI_VI_LOOP_CMP(BODY) \
+  VI_CHECK_MSS(false); \
   VI_LOOP_CMP_BASE \
   if (sew == e8){ \
     VI_PARAMS(e8); \
@@ -655,6 +667,7 @@ static inline bool is_overlapped(const int astart, const int asize,
   VI_LOOP_CMP_END
 
 #define VI_VV_ULOOP_CMP(BODY) \
+  VI_CHECK_MSS(true); \
   VI_LOOP_CMP_BASE \
   if (sew == e8){ \
     VV_U_PARAMS(e8); \
@@ -672,6 +685,7 @@ static inline bool is_overlapped(const int astart, const int asize,
   VI_LOOP_CMP_END
 
 #define VI_VX_ULOOP_CMP(BODY) \
+  VI_CHECK_MSS(false); \
   VI_LOOP_CMP_BASE \
   if (sew == e8){ \
     VX_U_PARAMS(e8); \
@@ -689,6 +703,7 @@ static inline bool is_overlapped(const int astart, const int asize,
   VI_LOOP_CMP_END
 
 #define VI_VI_ULOOP_CMP(BODY) \
+  VI_CHECK_MSS(false); \
   VI_LOOP_CMP_BASE \
   if (sew == e8){ \
     VI_U_PARAMS(e8); \
@@ -1242,6 +1257,7 @@ VI_LOOP_END
 
 // carry/borrow bit loop
 #define VI_VV_LOOP_CARRY(BODY) \
+  VI_CHECK_MSS(true); \
   VI_LOOP_BASE \
     if (sew == e8){ \
       VV_CARRY_PARAMS(e8) \
@@ -1259,6 +1275,7 @@ VI_LOOP_END
   } \
 
 #define VI_XI_LOOP_CARRY(BODY) \
+  VI_CHECK_MSS(false); \
   VI_LOOP_BASE \
     if (sew == e8){ \
       XI_CARRY_PARAMS(e8) \
@@ -1597,7 +1614,8 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   DEBUG_RVV_FP_VF; \
   VI_VFP_LOOP_END
 
-#define VI_VFP_LOOP_CMP(BODY) \
+#define VI_VFP_LOOP_CMP(BODY, is_vs1) \
+  VI_CHECK_MSS(is_vs1); \
   VI_VFP_LOOP_CMP_BASE \
   BODY; \
   set_fp_exceptions; \

riscv/insns/vmfeq_vf.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_eq(vs2, rs1);
-})
+}, false)

riscv/insns/vmfeq_vv.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_eq(vs2, vs1);
-})
+}, true)

riscv/insns/vmfge_vf.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_le(rs1, vs2);
-})
+}, false)

riscv/insns/vmfgt_vf.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_lt(rs1, vs2);
-})
+}, false)

riscv/insns/vmfle_vf.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_le(vs2, rs1);
-})
+}, false)

riscv/insns/vmfle_vv.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_le(vs2, vs1);
-})
+}, true)

riscv/insns/vmflt_vf.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_lt(vs2, rs1);
-})
+}, false)

riscv/insns/vmflt_vv.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = f32_lt(vs2, vs1);
-})
+}, true)

riscv/insns/vmfne_vf.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = !f32_eq(vs2, rs1);
-})
+}, false)

riscv/insns/vmfne_vv.h

@@ -2,4 +2,4 @@
 VI_VFP_LOOP_CMP
 ({
   res = !f32_eq(vs2, vs1);
-})
+}, true)