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riscv-isa-sim
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Merge pull request #2338 from riscv-software-src/rename-dot 

Fix names of dot-product instructions
pull/2339/head
Andrew Waterman 4 weeks ago
committed by GitHub
parent
f7bd55744a 3e6a4ea28b
commit
b0093c40c3
No known key found for this signature in database GPG Key ID: B5690EEEBB952194
24 changed files with 133 additions and 101 deletions
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  1. 42
      disasm/disasm.cc
  2. 2
      disasm/isa_parser.cc
  3. 110
      riscv/encoding.h
  4. 0
      riscv/insns/vdot4a_common.h
  5. 4
      riscv/insns/vdot4a_vv.h
  6. 4
      riscv/insns/vdot4a_vx.h
  7. 4
      riscv/insns/vdot4asu_vv.h
  8. 4
      riscv/insns/vdot4asu_vx.h
  9. 4
      riscv/insns/vdot4au_vv.h
  10. 4
      riscv/insns/vdot4au_vx.h
  11. 4
      riscv/insns/vdot4aus_vx.h
  12. 0
      riscv/insns/vfbdota_vv.h
  13. 0
      riscv/insns/vfqwbdota_alt_vv.h
  14. 0
      riscv/insns/vfqwbdota_vv.h
  15. 0
      riscv/insns/vfqwdota_alt_vv.h
  16. 0
      riscv/insns/vfqwdota_vv.h
  17. 0
      riscv/insns/vfwbdota_vv.h
  18. 0
      riscv/insns/vfwdota_vv.h
  19. 0
      riscv/insns/vqwbdotas_vv.h
  20. 0
      riscv/insns/vqwbdotau_vv.h
  21. 0
      riscv/insns/vqwdotas_vv.h
  22. 0
      riscv/insns/vqwdotau_vv.h
  23. 2
      riscv/isa_parser.h
  24. 50
      riscv/riscv.mk.in

42
disasm/disasm.cc
View File

@ -1952,11 +1952,43 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
DISASM_OPIV_MULTIPLYADD__X__INSN(vwmaccus, 1);
DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccsu, 0);
if (ext_enabled(EXT_ZVQDOTQ)) {
DISASM_OPIV_VX__INSN(vqdot, 0);
DISASM_OPIV_VX__INSN(vqdotu, 0);
DISASM_OPIV_VX__INSN(vqdotsu, 0);
DISASM_OPIV__X__INSN(vqdotus, 0);
if (ext_enabled(EXT_ZVDOT4A)) {
DISASM_OPIV_VX__INSN(vdot4a, 0);
DISASM_OPIV_VX__INSN(vdot4au, 0);
DISASM_OPIV_VX__INSN(vdot4asu, 0);
DISASM_OPIV__X__INSN(vdot4aus, 0);
}
if (ext_enabled(EXT_ZVQWBDOTA8I) || ext_enabled(EXT_ZVQWBDOTA16I)) {
DEFINE_VECTOR_VV(vqwbdotau_vv);
DEFINE_VECTOR_VV(vqwbdotas_vv);
}
if (ext_enabled(EXT_ZVFQWBDOTA8F)) {
DEFINE_VECTOR_VV(vfqwbdota_vv);
DEFINE_VECTOR_VV(vfqwbdota_alt_vv);
}
if (ext_enabled(EXT_ZVFWBDOTA16BF)) {
DEFINE_VECTOR_VV(vfwbdota_vv);
}
if (ext_enabled(EXT_ZVFBDOTA32F)) {
DEFINE_VECTOR_VV(vfbdota_vv);
}
if (ext_enabled(EXT_ZVQWDOTA8I) || ext_enabled(EXT_ZVQWDOTA16I)) {
DEFINE_VECTOR_VV(vqwdotau_vv);
DEFINE_VECTOR_VV(vqwdotas_vv);
}
if (ext_enabled(EXT_ZVFQWDOTA8F)) {
DEFINE_VECTOR_VV(vfqwdota_vv);
DEFINE_VECTOR_VV(vfqwdota_alt_vv);
}
if (ext_enabled(EXT_ZVFWDOTA16BF)) {
DEFINE_VECTOR_VV(vfwdota_vv);
}
#undef DISASM_OPIV_VXI_INSN

2
disasm/isa_parser.cc
View File

@ -193,7 +193,7 @@ static const extension_info_t extension_infos[] = {
{"zvksg", {EXT_ZVKB, EXT_ZVKG, EXT_ZVKSED, EXT_ZVKSH}},
{"zvksed", {EXT_ZVKSED}},
{"zvksh", {EXT_ZVKSH}},
{"zvqdotq", {EXT_ZVQDOTQ}},
{"zvdot4a", {EXT_ZVDOT4A}},
{"zvqwbdota8i", {EXT_ZVQWBDOTA8I}},
{"zvqwbdota16i", {EXT_ZVQWBDOTA16I}},
{"zvfqwbdota8f", {EXT_ZVFQWBDOTA8F}},

110
riscv/encoding.h
View File

@ -4,7 +4,7 @@
/*
* This file is auto-generated by running 'make' in
* https://github.com/riscv/riscv-opcodes (0a08518)
* https://github.com/riscv/riscv-opcodes (ec5d992)
*/
#ifndef RISCV_CSR_ENCODING_H
@ -2895,12 +2895,26 @@
#define MASK_VDIVU_VV 0xfc00707f
#define MATCH_VDIVU_VX 0x80006057
#define MASK_VDIVU_VX 0xfc00707f
#define MATCH_VDOT4A_VV 0xb0002057
#define MASK_VDOT4A_VV 0xfc00707f
#define MATCH_VDOT4A_VX 0xb0006057
#define MASK_VDOT4A_VX 0xfc00707f
#define MATCH_VDOT4ASU_VV 0xa8002057
#define MASK_VDOT4ASU_VV 0xfc00707f
#define MATCH_VDOT4ASU_VX 0xa8006057
#define MASK_VDOT4ASU_VX 0xfc00707f
#define MATCH_VDOT4AU_VV 0xa0002057
#define MASK_VDOT4AU_VV 0xfc00707f
#define MATCH_VDOT4AU_VX 0xa0006057
#define MASK_VDOT4AU_VX 0xfc00707f
#define MATCH_VDOT4AUS_VX 0xb8006057
#define MASK_VDOT4AUS_VX 0xfc00707f
#define MATCH_VFADD_VF 0x5057
#define MASK_VFADD_VF 0xfc00707f
#define MATCH_VFADD_VV 0x1057
#define MASK_VFADD_VV 0xfc00707f
#define MATCH_VFBDOT_VV 0xac001077
#define MASK_VFBDOT_VV 0xfc00707f
#define MATCH_VFBDOTA_VV 0xac001077
#define MASK_VFBDOTA_VV 0xfc00707f
#define MATCH_VFCLASS_V 0x4c081057
#define MASK_VFCLASS_V 0xfc0ff07f
#define MATCH_VFCVT_F_X_V 0x48019057
@ -2999,14 +3013,14 @@
#define MASK_VFNMSUB_VF 0xfc00707f
#define MATCH_VFNMSUB_VV 0xac001057
#define MASK_VFNMSUB_VV 0xfc00707f
#define MATCH_VFQBDOT_ALT_VV 0xbc001077
#define MASK_VFQBDOT_ALT_VV 0xfc00707f
#define MATCH_VFQBDOT_VV 0xb8001077
#define MASK_VFQBDOT_VV 0xfc00707f
#define MATCH_VFQLDOT_ALT_VV 0x9c001077
#define MASK_VFQLDOT_ALT_VV 0xfc00707f
#define MATCH_VFQLDOT_VV 0x98001077
#define MASK_VFQLDOT_VV 0xfc00707f
#define MATCH_VFQWBDOTA_ALT_VV 0xbc001077
#define MASK_VFQWBDOTA_ALT_VV 0xfc00707f
#define MATCH_VFQWBDOTA_VV 0xb8001077
#define MASK_VFQWBDOTA_VV 0xfc00707f
#define MATCH_VFQWDOTA_ALT_VV 0x9c001077
#define MASK_VFQWDOTA_ALT_VV 0xfc00707f
#define MATCH_VFQWDOTA_VV 0x98001077
#define MASK_VFQWDOTA_VV 0xfc00707f
#define MATCH_VFRDIV_VF 0x84005057
#define MASK_VFRDIV_VF 0xfc00707f
#define MATCH_VFREC7_V 0x4c029057
@ -3053,8 +3067,8 @@
#define MASK_VFWADD_WF 0xfc00707f
#define MATCH_VFWADD_WV 0xd0001057
#define MASK_VFWADD_WV 0xfc00707f
#define MATCH_VFWBDOT_VV 0xb0001077
#define MASK_VFWBDOT_VV 0xfc00707f
#define MATCH_VFWBDOTA_VV 0xb0001077
#define MASK_VFWBDOTA_VV 0xfc00707f
#define MATCH_VFWCVT_F_F_V 0x48061057
#define MASK_VFWCVT_F_F_V 0xfc0ff07f
#define MATCH_VFWCVT_F_X_V 0x48059057
@ -3071,8 +3085,8 @@
#define MASK_VFWCVT_XU_F_V 0xfc0ff07f
#define MATCH_VFWCVTBF16_F_F_V 0x48069057
#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
#define MATCH_VFWLDOT_VV 0x90001077
#define MASK_VFWLDOT_VV 0xfc00707f
#define MATCH_VFWDOTA_VV 0x90001077
#define MASK_VFWDOTA_VV 0xfc00707f
#define MATCH_VFWMACC_VF 0xf0005057
#define MASK_VFWMACC_VF 0xfc00707f
#define MATCH_VFWMACC_VV 0xf0001057
@ -3399,28 +3413,14 @@
#define MASK_VPAIRE_VV 0xfc00707f
#define MATCH_VPAIRO_VV 0x3c002057
#define MASK_VPAIRO_VV 0xfc00707f
#define MATCH_VQBDOTS_VV 0xbc000077
#define MASK_VQBDOTS_VV 0xfc00707f
#define MATCH_VQBDOTU_VV 0xb8000077
#define MASK_VQBDOTU_VV 0xfc00707f
#define MATCH_VQDOT_VV 0xb0002057
#define MASK_VQDOT_VV 0xfc00707f
#define MATCH_VQDOT_VX 0xb0006057
#define MASK_VQDOT_VX 0xfc00707f
#define MATCH_VQDOTSU_VV 0xa8002057
#define MASK_VQDOTSU_VV 0xfc00707f
#define MATCH_VQDOTSU_VX 0xa8006057
#define MASK_VQDOTSU_VX 0xfc00707f
#define MATCH_VQDOTU_VV 0xa0002057
#define MASK_VQDOTU_VV 0xfc00707f
#define MATCH_VQDOTU_VX 0xa0006057
#define MASK_VQDOTU_VX 0xfc00707f
#define MATCH_VQDOTUS_VX 0xb8006057
#define MASK_VQDOTUS_VX 0xfc00707f
#define MATCH_VQLDOTS_VV 0x9c000077
#define MASK_VQLDOTS_VV 0xfc00707f
#define MATCH_VQLDOTU_VV 0x98000077
#define MASK_VQLDOTU_VV 0xfc00707f
#define MATCH_VQWBDOTAS_VV 0xbc000077
#define MASK_VQWBDOTAS_VV 0xfc00707f
#define MATCH_VQWBDOTAU_VV 0xb8000077
#define MASK_VQWBDOTAU_VV 0xfc00707f
#define MATCH_VQWDOTAS_VV 0x9c000077
#define MASK_VQWDOTAS_VV 0xfc00707f
#define MATCH_VQWDOTAU_VV 0x98000077
#define MASK_VQWDOTAU_VV 0xfc00707f
#define MATCH_VREDAND_VS 0x4002057
#define MASK_VREDAND_VS 0xfc00707f
#define MATCH_VREDMAX_VS 0x1c002057
@ -5540,9 +5540,16 @@ DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
DECLARE_INSN(vdot4a_vv, MATCH_VDOT4A_VV, MASK_VDOT4A_VV)
DECLARE_INSN(vdot4a_vx, MATCH_VDOT4A_VX, MASK_VDOT4A_VX)
DECLARE_INSN(vdot4asu_vv, MATCH_VDOT4ASU_VV, MASK_VDOT4ASU_VV)
DECLARE_INSN(vdot4asu_vx, MATCH_VDOT4ASU_VX, MASK_VDOT4ASU_VX)
DECLARE_INSN(vdot4au_vv, MATCH_VDOT4AU_VV, MASK_VDOT4AU_VV)
DECLARE_INSN(vdot4au_vx, MATCH_VDOT4AU_VX, MASK_VDOT4AU_VX)
DECLARE_INSN(vdot4aus_vx, MATCH_VDOT4AUS_VX, MASK_VDOT4AUS_VX)
DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF)
DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV)
DECLARE_INSN(vfbdot_vv, MATCH_VFBDOT_VV, MASK_VFBDOT_VV)
DECLARE_INSN(vfbdota_vv, MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV)
DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V)
DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V)
@ -5592,10 +5599,10 @@ DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF)
DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV)
DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF)
DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV)
DECLARE_INSN(vfqbdot_alt_vv, MATCH_VFQBDOT_ALT_VV, MASK_VFQBDOT_ALT_VV)
DECLARE_INSN(vfqbdot_vv, MATCH_VFQBDOT_VV, MASK_VFQBDOT_VV)
DECLARE_INSN(vfqldot_alt_vv, MATCH_VFQLDOT_ALT_VV, MASK_VFQLDOT_ALT_VV)
DECLARE_INSN(vfqldot_vv, MATCH_VFQLDOT_VV, MASK_VFQLDOT_VV)
DECLARE_INSN(vfqwbdota_alt_vv, MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV)
DECLARE_INSN(vfqwbdota_vv, MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV)
DECLARE_INSN(vfqwdota_alt_vv, MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV)
DECLARE_INSN(vfqwdota_vv, MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV)
DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF)
DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V)
DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS)
@ -5619,7 +5626,7 @@ DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF)
DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)
DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF)
DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV)
DECLARE_INSN(vfwbdot_vv, MATCH_VFWBDOT_VV, MASK_VFWBDOT_VV)
DECLARE_INSN(vfwbdota_vv, MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV)
DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V)
DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V)
DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V)
@ -5628,7 +5635,7 @@ DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V)
DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V)
DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
DECLARE_INSN(vfwldot_vv, MATCH_VFWLDOT_VV, MASK_VFWLDOT_VV)
DECLARE_INSN(vfwdota_vv, MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV)
DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF)
DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV)
DECLARE_INSN(vfwmaccbf16_vf, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
@ -5792,17 +5799,10 @@ DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX)
DECLARE_INSN(vpaire_vv, MATCH_VPAIRE_VV, MASK_VPAIRE_VV)
DECLARE_INSN(vpairo_vv, MATCH_VPAIRO_VV, MASK_VPAIRO_VV)
DECLARE_INSN(vqbdots_vv, MATCH_VQBDOTS_VV, MASK_VQBDOTS_VV)
DECLARE_INSN(vqbdotu_vv, MATCH_VQBDOTU_VV, MASK_VQBDOTU_VV)
DECLARE_INSN(vqdot_vv, MATCH_VQDOT_VV, MASK_VQDOT_VV)
DECLARE_INSN(vqdot_vx, MATCH_VQDOT_VX, MASK_VQDOT_VX)
DECLARE_INSN(vqdotsu_vv, MATCH_VQDOTSU_VV, MASK_VQDOTSU_VV)
DECLARE_INSN(vqdotsu_vx, MATCH_VQDOTSU_VX, MASK_VQDOTSU_VX)
DECLARE_INSN(vqdotu_vv, MATCH_VQDOTU_VV, MASK_VQDOTU_VV)
DECLARE_INSN(vqdotu_vx, MATCH_VQDOTU_VX, MASK_VQDOTU_VX)
DECLARE_INSN(vqdotus_vx, MATCH_VQDOTUS_VX, MASK_VQDOTUS_VX)
DECLARE_INSN(vqldots_vv, MATCH_VQLDOTS_VV, MASK_VQLDOTS_VV)
DECLARE_INSN(vqldotu_vv, MATCH_VQLDOTU_VV, MASK_VQLDOTU_VV)
DECLARE_INSN(vqwbdotas_vv, MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV)
DECLARE_INSN(vqwbdotau_vv, MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV)
DECLARE_INSN(vqwdotas_vv, MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV)
DECLARE_INSN(vqwdotau_vv, MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV)
DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)
DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS)
DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS)

0
riscv/insns/vqdot_common.h → riscv/insns/vdot4a_common.h
View File

4
riscv/insns/vqdot_vv.h → riscv/insns/vdot4a_vv.h
View File

@ -1,7 +1,7 @@
// vqdot.vv vd, vs2, vs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VV_LOOP

4
riscv/insns/vqdot_vx.h → riscv/insns/vdot4a_vx.h
View File

@ -1,7 +1,7 @@
// vqdot.vx vd, vs2, rs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VX_LOOP

4
riscv/insns/vqdotsu_vv.h → riscv/insns/vdot4asu_vv.h
View File

@ -1,7 +1,7 @@
// vqdotsu.vv vd, vs2, vs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VV_LOOP

4
riscv/insns/vqdotsu_vx.h → riscv/insns/vdot4asu_vx.h
View File

@ -1,7 +1,7 @@
// vqdotsu.vx vd, vs2, rs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VX_LOOP

4
riscv/insns/vqdotu_vv.h → riscv/insns/vdot4au_vv.h
View File

@ -1,7 +1,7 @@
// vqdotu.vv vd, vs2, vs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VV_LOOP

4
riscv/insns/vqdotu_vx.h → riscv/insns/vdot4au_vx.h
View File

@ -1,7 +1,7 @@
// vqdotu.vx vd, vs2, rs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VX_LOOP

4
riscv/insns/vqdotus_vx.h → riscv/insns/vdot4aus_vx.h
View File

@ -1,7 +1,7 @@
// vqdotus.vx vd, vs2, rs1, vm
#include "vqdot_common.h"
#include "vdot4a_common.h"
require_extension(EXT_ZVQDOTQ);
require_extension(EXT_ZVDOT4A);
require(P.VU.vsew == e32);
VI_VX_LOOP

0
riscv/insns/vfbdot_vv.h → riscv/insns/vfbdota_vv.h
View File

0
riscv/insns/vfqbdot_alt_vv.h → riscv/insns/vfqwbdota_alt_vv.h
View File

0
riscv/insns/vfqbdot_vv.h → riscv/insns/vfqwbdota_vv.h
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0
riscv/insns/vfqldot_alt_vv.h → riscv/insns/vfqwdota_alt_vv.h
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0
riscv/insns/vfqldot_vv.h → riscv/insns/vfqwdota_vv.h
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0
riscv/insns/vfwbdot_vv.h → riscv/insns/vfwbdota_vv.h
View File

0
riscv/insns/vfwldot_vv.h → riscv/insns/vfwdota_vv.h
View File

0
riscv/insns/vqbdots_vv.h → riscv/insns/vqwbdotas_vv.h
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0
riscv/insns/vqbdotu_vv.h → riscv/insns/vqwbdotau_vv.h
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0
riscv/insns/vqldots_vv.h → riscv/insns/vqwdotas_vv.h
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0
riscv/insns/vqldotu_vv.h → riscv/insns/vqwdotau_vv.h
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2
riscv/isa_parser.h
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@ -81,7 +81,7 @@ typedef enum {
EXT_ZVKNHB,
EXT_ZVKSED,
EXT_ZVKSH,
EXT_ZVQDOTQ,
EXT_ZVDOT4A,
EXT_ZVQWBDOTA8I,
EXT_ZVQWBDOTA16I,
EXT_ZVFQWBDOTA8F,

50
riscv/riscv.mk.in
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@ -867,21 +867,21 @@ riscv_insn_ext_v_ctrl = \
vsetvli \
vsetvl \
riscv_insn_ext_zvqdotq = \
vqdot_vv \
vqdot_vx \
vqdotu_vv \
vqdotu_vx \
vqdotsu_vv \
vqdotsu_vx \
vqdotus_vx \
riscv_insn_ext_zvdot4a = \
vdot4a_vv \
vdot4a_vx \
vdot4au_vv \
vdot4au_vx \
vdot4asu_vv \
vdot4asu_vx \
vdot4aus_vx \
riscv_insn_ext_v = \
$(riscv_insn_ext_v_alu_fp) \
$(riscv_insn_ext_v_alu_int) \
$(riscv_insn_ext_v_ctrl) \
$(riscv_insn_ext_v_ldst) \
$(riscv_insn_ext_zvqdotq) \
$(riscv_insn_ext_zvdot4a) \
riscv_insn_ext_h = \
hfence_gvma \
@ -1087,20 +1087,20 @@ riscv_insn_ext_zvksh = \
vsm3c_vi \
vsm3me_vv \
riscv_insn_ext_zvbdot = \
vqbdotu_vv \
vqbdots_vv \
vfwbdot_vv \
vfbdot_vv \
vfqbdot_vv \
vfqbdot_alt_vv \
riscv_insn_ext_zvldot = \
vqldotu_vv \
vqldots_vv \
vfwldot_vv \
vfqldot_vv \
vfqldot_alt_vv \
riscv_insn_ext_zvbdota = \
vfbdota_vv \
vfqwbdota_alt_vv \
vfqwbdota_vv \
vfwbdota_vv \
vqwbdotas_vv \
vqwbdotau_vv \
riscv_insn_ext_zvdota = \
vfqwdota_alt_vv \
vfqwdota_vv \
vfwdota_vv \
vqwdotas_vv \
vqwdotau_vv \
riscv_insn_ext_zimop = \
mop_r_N \
@ -1789,8 +1789,8 @@ riscv_insn_list = \
$(riscv_insn_ext_zfh_zfa) \
$(riscv_insn_ext_zicond) \
$(riscv_insn_ext_zvk) \
$(riscv_insn_ext_zvbdot) \
$(riscv_insn_ext_zvldot) \
$(riscv_insn_ext_zvbdota) \
$(riscv_insn_ext_zvdota) \
$(riscv_insn_ext_zvabd) \
$(riscv_insn_ext_zvzip) \
$(riscv_insn_priv) \

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