From ae9888e50806837a3b6a39293c1014d9c7c37c56 Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Sun, 27 Aug 2023 14:13:13 -0500
Subject: [PATCH] check g-stage write perm and set D bit in g-stage pte for
 vs-stage pte A/D updates

---
 riscv/mmu.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 285ef6d3..1473e890 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -536,6 +536,9 @@ reg_t mmu_t::walk(mem_access_info_t access_info)
 
       if ((pte & ad) != ad) {
         if (hade) {
+          // Check for write permission to the first-stage PT in second-stage
+          // PTE and set the D bit in the second-stage PTE if needed
+          s2xlate(addr, base + idx * vm.ptesize, STORE, type, virt, false);
           // set accessed and possibly dirty bits.
           pte_store(pte_paddr, pte | ad, addr, virt, type, vm.ptesize);
         } else {