[sim] Bug fixes in shifts, plus a new test case

16 years ago · ae3bcd0a39
3 changed files with 3 additions and 3 deletions
--- a/riscv/insns/srav.h
+++ b/riscv/insns/srav.h
@ -1,2 +1,2 @@
 require64;
-RC = RB >> (RA & 0x3F);
+RC = sreg_t(RB) >> (RA & 0x3F);
--- a/riscv/insns/srlvw.h
+++ b/riscv/insns/srlvw.h
@ -1 +1 @@
-RC = sext32(RB >> (RA & 0x1F));
+RC = sext32((uint32_t)RB >> (RA & 0x1F));
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@ -1 +1 @@
-RC = sext32(RB >> SHAMT);
+RC = sext32((uint32_t)RB >> SHAMT);