diff --git a/riscv/common.h b/riscv/common.h
index a354ced0..b55657b0 100644
--- a/riscv/common.h
+++ b/riscv/common.h
@@ -19,4 +19,16 @@
 # define UNUSED
 #endif
 
+#ifndef __has_builtin
+# define __has_builtin(x) 0
+#endif
+
+#if __has_cpp_attribute(assume)
+# define assume(x) [[assume(x)]]
+#elif __has_builtin(__builtin_assume)
+# define assume(x) __builtin_assume(x)
+#else
+# define assume(x) ((void) 0)
+#endif
+
 #endif
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index c337d4a7..dd85f3d2 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -773,6 +773,8 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept {
     }
   }
 
+  proc->get_mmu()->flush_tlb();
+
   return basic_csr_t::unlogged_write(new_misa);
 }
 
diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
index 168e2dc8..12d564b8 100644
--- a/riscv/insn_template.cc
+++ b/riscv/insn_template.cc
@@ -6,7 +6,8 @@
 #define DECODE_MACRO_USAGE_LOGGED 0
 
 #define PROLOGUE \
-  reg_t npc = sext_xlen(pc + insn_length(OPCODE))
+  reg_t npc = sext_xlen(pc + insn_length(OPCODE)); \
+  if (!p->extension_enabled(EXT_ZCA)) assume(insn_length(OPCODE) % 4 == 0)
 
 #define EPILOGUE \
   trace_opcode(p, OPCODE, insn); \
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7e6f7c08..ffdaa190 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -662,6 +662,9 @@ reg_t processor_t::throw_instruction_address_misaligned(reg_t pc)
 
 insn_func_t processor_t::decode_insn(insn_t insn)
 {
+  if (!extension_enabled(EXT_ZCA) && insn_length(insn.bits()) % 4)
+    return &::illegal_instruction;
+
   // look up opcode in hash table
   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
   auto [hit, desc] = opcode_cache[idx].lookup(insn.bits());