[xcc, sim] branches now are next-PC-based, not PC-based

riscv/decode.h

@@ -141,8 +141,8 @@ union insn_t
 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 #define SHAMT insn.rtype.shamt
 #define TARGET insn.jtype.target
-#define BRANCH_TARGET (pc + (SIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET ((pc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
+#define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
+#define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction

riscv/execute.h

@@ -176,6 +176,11 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninj_d.h"
           break;
         }
+        if((insn.bits & 0xfe007fe0) == 0xd0006060)
+        {
+          #include "insns/div_d.h"
+          break;
+        }
         if((insn.bits & 0xfe007fe0) == 0xd0006820)
         {
           #include "insns/c_eq_d.h"
@@ -246,11 +251,6 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sqrt_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd0006060)
-        {
-          #include "insns/div_d.h"
-          break;
-        }
         if((insn.bits & 0xfe0fffe0) == 0xd00064c0)
         {
           #include "insns/cvt_d_w.h"
@@ -984,7 +984,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xffffffe0) == 0xf6001000)
         {
-          #include "insns/rdpc.h"
+          #include "insns/rdnpc.h"
           break;
         }
         #include "insns/unimp.h"