From a9dce622c3d6fb2b72a4ca6daebdacebfd55b274 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Thu, 28 Nov 2019 19:55:33 -0800
Subject: [PATCH] rvv: add vfxxx.vf float64 support

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 riscv/decode.h             | 12 ++++++++++--
 riscv/insns/vfadd_vf.h     |  5 ++++-
 riscv/insns/vfcvt_f_x_v.h  |  4 ++++
 riscv/insns/vfcvt_f_xu_v.h |  4 ++++
 riscv/insns/vfcvt_x_f_v.h  |  3 +++
 riscv/insns/vfdiv_vf.h     |  3 +++
 riscv/insns/vfmacc_vf.h    |  3 +++
 riscv/insns/vfmadd_vf.h    |  3 +++
 riscv/insns/vfmax_vf.h     |  3 +++
 riscv/insns/vfmin_vf.h     |  3 +++
 riscv/insns/vfmsac_vf.h    |  3 +++
 riscv/insns/vfmsub_vf.h    |  3 +++
 riscv/insns/vfmul_vf.h     |  3 +++
 riscv/insns/vfnmacc_vf.h   |  3 +++
 riscv/insns/vfnmadd_vf.h   |  3 +++
 riscv/insns/vfnmsac_vf.h   |  3 +++
 riscv/insns/vfnmsub_vf.h   |  3 +++
 riscv/insns/vfrdiv_vf.h    |  3 +++
 riscv/insns/vfrsub_vf.h    |  3 +++
 riscv/insns/vfsgnj_vf.h    |  3 +++
 riscv/insns/vfsgnjn_vf.h   |  3 +++
 riscv/insns/vfsgnjx_vf.h   |  3 +++
 riscv/insns/vfsub_vf.h     |  3 +++
 23 files changed, 79 insertions(+), 3 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index bdee8376..62e798eb 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1712,7 +1712,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_REDUCTION_END(e64)
 
-#define VI_VFP_VF_LOOP(BODY) \
+#define VI_VFP_VF_LOOP(BODY32, BODY64) \
   VI_CHECK_SSS(false); \
   VI_VFP_LOOP_BASE \
   switch(P.VU.vsew) { \
@@ -1720,7 +1720,15 @@ for (reg_t i = 0; i < vlmax; ++i) { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
       float32_t rs1 = f32(READ_FREG(rs1_num)); \
       float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
-      BODY; \
+      BODY32; \
+      set_fp_exceptions; \
+      break; \
+    }\
+    case e64: {\
+      float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
+      float64_t rs1 = f64(READ_FREG(rs1_num)); \
+      float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
+      BODY64; \
       set_fp_exceptions; \
       break; \
     }\
diff --git a/riscv/insns/vfadd_vf.h b/riscv/insns/vfadd_vf.h
index 60dec4a8..bdb7f75c 100644
--- a/riscv/insns/vfadd_vf.h
+++ b/riscv/insns/vfadd_vf.h
@@ -1,5 +1,8 @@
 // vfadd.vf vd, vs2, rs1
 VI_VFP_VF_LOOP
 ({
-    vd = f32_add(rs1, vs2);
+  vd = f32_add(rs1, vs2);
+},
+{
+  vd = f64_add(rs1, vs2);
 })
diff --git a/riscv/insns/vfcvt_f_x_v.h b/riscv/insns/vfcvt_f_x_v.h
index f6604fb9..fdaa697f 100644
--- a/riscv/insns/vfcvt_f_x_v.h
+++ b/riscv/insns/vfcvt_f_x_v.h
@@ -3,4 +3,8 @@ VI_VFP_VF_LOOP
 ({
   auto vs2_i = P.VU.elt<int32_t>(rs2_num, i);
   vd = i32_to_f32(vs2_i);
+},
+{
+  auto vs2_i = P.VU.elt<int64_t>(rs2_num, i);
+  vd = i64_to_f64(vs2_i);
 })
diff --git a/riscv/insns/vfcvt_f_xu_v.h b/riscv/insns/vfcvt_f_xu_v.h
index 2c845acd..01ea61ca 100644
--- a/riscv/insns/vfcvt_f_xu_v.h
+++ b/riscv/insns/vfcvt_f_xu_v.h
@@ -3,4 +3,8 @@ VI_VFP_VF_LOOP
 ({
   auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i);
   vd = ui32_to_f32(vs2_u);
+},
+{
+  auto vs2_u = P.VU.elt<uint64_t>(rs2_num, i);
+  vd = ui64_to_f64(vs2_u);
 })
diff --git a/riscv/insns/vfcvt_x_f_v.h b/riscv/insns/vfcvt_x_f_v.h
index a9eedc45..96bc481d 100644
--- a/riscv/insns/vfcvt_x_f_v.h
+++ b/riscv/insns/vfcvt_x_f_v.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true);
+},
+{
+  P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm, true);
 })
diff --git a/riscv/insns/vfdiv_vf.h b/riscv/insns/vfdiv_vf.h
index 2b8124ce..ce217304 100644
--- a/riscv/insns/vfdiv_vf.h
+++ b/riscv/insns/vfdiv_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_div(vs2, rs1);
+},
+{
+  vd = f64_div(vs2, rs1);
 })
diff --git a/riscv/insns/vfmacc_vf.h b/riscv/insns/vfmacc_vf.h
index 5013d349..fca41840 100644
--- a/riscv/insns/vfmacc_vf.h
+++ b/riscv/insns/vfmacc_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, vs2, vd);
+},
+{
+  vd = f64_mulAdd(rs1, vs2, vd);
 })
diff --git a/riscv/insns/vfmadd_vf.h b/riscv/insns/vfmadd_vf.h
index 920c3922..7707daec 100644
--- a/riscv/insns/vfmadd_vf.h
+++ b/riscv/insns/vfmadd_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(vd, rs1, vs2);
+},
+{
+  vd = f64_mulAdd(vd, rs1, vs2);
 })
diff --git a/riscv/insns/vfmax_vf.h b/riscv/insns/vfmax_vf.h
index eb70e482..a8df880f 100644
--- a/riscv/insns/vfmax_vf.h
+++ b/riscv/insns/vfmax_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_max(vs2, rs1);
+},
+{
+  vd = f64_max(vs2, rs1);
 })
diff --git a/riscv/insns/vfmin_vf.h b/riscv/insns/vfmin_vf.h
index bf06638a..a55462b6 100644
--- a/riscv/insns/vfmin_vf.h
+++ b/riscv/insns/vfmin_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_min(vs2, rs1);
+},
+{
+  vd = f64_min(vs2, rs1);
 })
diff --git a/riscv/insns/vfmsac_vf.h b/riscv/insns/vfmsac_vf.h
index 23661b33..0f42560e 100644
--- a/riscv/insns/vfmsac_vf.h
+++ b/riscv/insns/vfmsac_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfmsub_vf.h b/riscv/insns/vfmsub_vf.h
index 2328d070..bd968e3d 100644
--- a/riscv/insns/vfmsub_vf.h
+++ b/riscv/insns/vfmsub_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(vd, rs1, f32(vs2.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(vd, rs1, f64(vs2.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfmul_vf.h b/riscv/insns/vfmul_vf.h
index 086b6d83..9e7d481a 100644
--- a/riscv/insns/vfmul_vf.h
+++ b/riscv/insns/vfmul_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mul(vs2, rs1);
+},
+{
+  vd = f64_mul(vs2, rs1);
 })
diff --git a/riscv/insns/vfnmacc_vf.h b/riscv/insns/vfnmacc_vf.h
index 04a31bf2..da58d3aa 100644
--- a/riscv/insns/vfnmacc_vf.h
+++ b/riscv/insns/vfnmacc_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), f32(vd.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(rs1, f64(vs2.v ^ F64_SIGN), f64(vd.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfnmadd_vf.h b/riscv/insns/vfnmadd_vf.h
index f8f3b832..b26f3775 100644
--- a/riscv/insns/vfnmadd_vf.h
+++ b/riscv/insns/vfnmadd_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, f32(vs2.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), rs1, f64(vs2.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfnmsac_vf.h b/riscv/insns/vfnmsac_vf.h
index c3dc12c4..b78d0cac 100644
--- a/riscv/insns/vfnmsac_vf.h
+++ b/riscv/insns/vfnmsac_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), vd);
+},
+{
+  vd = f64_mulAdd(rs1, f64(vs2.v ^ F64_SIGN), vd);
 })
diff --git a/riscv/insns/vfnmsub_vf.h b/riscv/insns/vfnmsub_vf.h
index 1879b9eb..6c6dc27d 100644
--- a/riscv/insns/vfnmsub_vf.h
+++ b/riscv/insns/vfnmsub_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, vs2);
+},
+{
+  vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), rs1, vs2);
 })
diff --git a/riscv/insns/vfrdiv_vf.h b/riscv/insns/vfrdiv_vf.h
index 49e42937..73ec5346 100644
--- a/riscv/insns/vfrdiv_vf.h
+++ b/riscv/insns/vfrdiv_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_div(rs1, vs2);
+},
+{
+  vd = f64_div(rs1, vs2);
 })
diff --git a/riscv/insns/vfrsub_vf.h b/riscv/insns/vfrsub_vf.h
index ee8ac838..d9a19863 100644
--- a/riscv/insns/vfrsub_vf.h
+++ b/riscv/insns/vfrsub_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_sub(rs1, vs2);
+},
+{
+  vd = f64_sub(rs1, vs2);
 })
diff --git a/riscv/insns/vfsgnj_vf.h b/riscv/insns/vfsgnj_vf.h
index d93f175d..c7f731ba 100644
--- a/riscv/insns/vfsgnj_vf.h
+++ b/riscv/insns/vfsgnj_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = fsgnj32(vs2.v, rs1.v, false, false);
+},
+{
+  vd = fsgnj64(vs2.v, rs1.v, false, false);
 })
diff --git a/riscv/insns/vfsgnjn_vf.h b/riscv/insns/vfsgnjn_vf.h
index 303ec760..45117481 100644
--- a/riscv/insns/vfsgnjn_vf.h
+++ b/riscv/insns/vfsgnjn_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = fsgnj32(vs2.v, rs1.v, true, false);
+},
+{
+  vd = fsgnj64(vs2.v, rs1.v, true, false);
 })
diff --git a/riscv/insns/vfsgnjx_vf.h b/riscv/insns/vfsgnjx_vf.h
index 93f43033..c4230600 100644
--- a/riscv/insns/vfsgnjx_vf.h
+++ b/riscv/insns/vfsgnjx_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = fsgnj32(vs2.v, rs1.v, false, true);
+},
+{
+  vd = fsgnj64(vs2.v, rs1.v, false, true);
 })
diff --git a/riscv/insns/vfsub_vf.h b/riscv/insns/vfsub_vf.h
index 38d6acc6..a4702d04 100644
--- a/riscv/insns/vfsub_vf.h
+++ b/riscv/insns/vfsub_vf.h
@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_sub(vs2, rs1);
+},
+{
+  vd = f64_sub(vs2, rs1);
 })