rvv: add vfxxx.vf float64 support

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/decode.h

@@ -1712,7 +1712,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_REDUCTION_END(e64)
 
-#define VI_VFP_VF_LOOP(BODY) \
+#define VI_VFP_VF_LOOP(BODY32, BODY64) \
   VI_CHECK_SSS(false); \
   VI_VFP_LOOP_BASE \
   switch(P.VU.vsew) { \
@@ -1720,7 +1720,15 @@ for (reg_t i = 0; i < vlmax; ++i) { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
       float32_t rs1 = f32(READ_FREG(rs1_num)); \
       float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
-      BODY; \
+      BODY32; \
+      set_fp_exceptions; \
+      break; \
+    }\
+    case e64: {\
+      float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
+      float64_t rs1 = f64(READ_FREG(rs1_num)); \
+      float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
+      BODY64; \
       set_fp_exceptions; \
       break; \
     }\

riscv/insns/vfadd_vf.h

@@ -1,5 +1,8 @@
 // vfadd.vf vd, vs2, rs1
 VI_VFP_VF_LOOP
 ({
-    vd = f32_add(rs1, vs2);
+  vd = f32_add(rs1, vs2);
+},
+{
+  vd = f64_add(rs1, vs2);
 })

riscv/insns/vfcvt_f_x_v.h

@@ -3,4 +3,8 @@ VI_VFP_VF_LOOP
 ({
   auto vs2_i = P.VU.elt<int32_t>(rs2_num, i);
   vd = i32_to_f32(vs2_i);
+},
+{
+  auto vs2_i = P.VU.elt<int64_t>(rs2_num, i);
+  vd = i64_to_f64(vs2_i);
 })

riscv/insns/vfcvt_f_xu_v.h

@@ -3,4 +3,8 @@ VI_VFP_VF_LOOP
 ({
   auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i);
   vd = ui32_to_f32(vs2_u);
+},
+{
+  auto vs2_u = P.VU.elt<uint64_t>(rs2_num, i);
+  vd = ui64_to_f64(vs2_u);
 })

riscv/insns/vfcvt_x_f_v.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true);
+},
+{
+  P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm, true);
 })

riscv/insns/vfdiv_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_div(vs2, rs1);
+},
+{
+  vd = f64_div(vs2, rs1);
 })

riscv/insns/vfmacc_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, vs2, vd);
+},
+{
+  vd = f64_mulAdd(rs1, vs2, vd);
 })

riscv/insns/vfmadd_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(vd, rs1, vs2);
+},
+{
+  vd = f64_mulAdd(vd, rs1, vs2);
 })

riscv/insns/vfmax_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_max(vs2, rs1);
+},
+{
+  vd = f64_max(vs2, rs1);
 })

riscv/insns/vfmin_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_min(vs2, rs1);
+},
+{
+  vd = f64_min(vs2, rs1);
 })

riscv/insns/vfmsac_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN));
 })

riscv/insns/vfmsub_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(vd, rs1, f32(vs2.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(vd, rs1, f64(vs2.v ^ F64_SIGN));
 })

riscv/insns/vfmul_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mul(vs2, rs1);
+},
+{
+  vd = f64_mul(vs2, rs1);
 })

riscv/insns/vfnmacc_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), f32(vd.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(rs1, f64(vs2.v ^ F64_SIGN), f64(vd.v ^ F64_SIGN));
 })

riscv/insns/vfnmadd_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, f32(vs2.v ^ F32_SIGN));
+},
+{
+  vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), rs1, f64(vs2.v ^ F64_SIGN));
 })

riscv/insns/vfnmsac_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), vd);
+},
+{
+  vd = f64_mulAdd(rs1, f64(vs2.v ^ F64_SIGN), vd);
 })

riscv/insns/vfnmsub_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, vs2);
+},
+{
+  vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), rs1, vs2);
 })

riscv/insns/vfrdiv_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_div(rs1, vs2);
+},
+{
+  vd = f64_div(rs1, vs2);
 })

riscv/insns/vfrsub_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_sub(rs1, vs2);
+},
+{
+  vd = f64_sub(rs1, vs2);
 })

riscv/insns/vfsgnj_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = fsgnj32(vs2.v, rs1.v, false, false);
+},
+{
+  vd = fsgnj64(vs2.v, rs1.v, false, false);
 })

riscv/insns/vfsgnjn_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = fsgnj32(vs2.v, rs1.v, true, false);
+},
+{
+  vd = fsgnj64(vs2.v, rs1.v, true, false);
 })

riscv/insns/vfsgnjx_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = fsgnj32(vs2.v, rs1.v, false, true);
+},
+{
+  vd = fsgnj64(vs2.v, rs1.v, false, true);
 })

riscv/insns/vfsub_vf.h

@@ -2,4 +2,7 @@
 VI_VFP_VF_LOOP
 ({
   vd = f32_sub(vs2, rs1);
+},
+{
+  vd = f64_sub(vs2, rs1);
 })