Merge pull request #613 from chihminchao/rvv-fix-2020-12-04

Rvv fix 2020 12 04

riscv/decode.h

@@ -1864,6 +1864,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   require_vm; \
   reg_t from = P.VU.vsew / div; \
   require(from >= e8 && from <= e64); \
+  require(((float)P.VU.vflmul / div) >= ((float)P.VU.vsew_min / P.VU.ELEN)); \
   require_align(insn.rd(), P.VU.vflmul); \
   require_align(insn.rs2(), P.VU.vflmul / div); \
   if ((P.VU.vflmul / div) < 1) { \

riscv/processor.cc

@@ -397,7 +397,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
 
     vill = !(vflmul >= 0.125 && vflmul <= 8)
            || vsew > ELEN
-           || vflmul < ((float)vsew / ELEN)
+           || vflmul < ((float)vsew_min / ELEN)
            || vediv != 1
            || (newType >> 8) != 0;
 

riscv/processor.h

@@ -488,6 +488,7 @@ public:
       reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
       reg_t vma, vta;
       reg_t vediv, vsew;
+      const reg_t vsew_min = 8; // the narrowest supported SEW value at LMUL=1
       float vflmul;
       reg_t ELEN, VLEN;
       bool vill;