riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

AIA: Add RV32-only hviph, hidelegh, vsieh, and vsiph CSRs

pull/1988/head
YenHaoChen 2 years ago
committed by Binno
parent
990454eda9
commit
a74392f5bc
1 changed files with 20 additions and 4 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 24
      riscv/csr_init.cc

24
riscv/csr_init.cc
View File

@ -145,25 +145,35 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
nonvirtual_sip = std::make_shared<sip_csr_t>(proc, CSR_SIP, sip_sie_accr);
auto vsip = std::make_shared<mip_proxy_csr_t>(proc, CSR_VSIP, vsip_vsie_accr);
add_hypervisor_csr(CSR_VSIP, vsip);
auto sip = std::make_shared<virtualized_csr_t>(proc, nonvirtual_sip, vsip);
if (xlen == 32 && proc->extension_enabled_const(EXT_SSAIA)) {
add_hypervisor_csr(CSR_VSIP, std::make_shared<rv32_low_csr_t>(proc, CSR_VSIP, vsip));
add_hypervisor_csr(CSR_VSIPH, std::make_shared<rv32_high_csr_t>(proc, CSR_VSIPH, vsip));
add_supervisor_csr(CSR_SIP, std::make_shared<rv32_low_csr_t>(proc, CSR_SIP, sip));
add_supervisor_csr(CSR_SIPH, std::make_shared<rv32_high_csr_t>(proc, CSR_SIPH, sip));
} else {
add_hypervisor_csr(CSR_VSIP, vsip);
add_supervisor_csr(CSR_SIP, sip);
}
add_hypervisor_csr(CSR_HIP, std::make_shared<mip_proxy_csr_t>(proc, CSR_HIP, hip_hie_accr));
add_hypervisor_csr(CSR_HVIP, hvip = std::make_shared<hvip_csr_t>(proc, CSR_HVIP, 0));
hvip = std::make_shared<hvip_csr_t>(proc, CSR_HVIP, 0);
if (xlen == 32 && proc->extension_enabled_const(EXT_SSAIA)) {
add_hypervisor_csr(CSR_HVIP, std::make_shared<rv32_low_csr_t>(proc, CSR_HVIP, hvip));
add_hypervisor_csr(CSR_HVIPH, std::make_shared<rv32_high_csr_t>(proc, CSR_HVIPH, hvip));
} else {
add_hypervisor_csr(CSR_HVIP, hvip);
}
nonvirtual_sie = std::make_shared<sie_csr_t>(proc, CSR_SIE, sip_sie_accr);
auto vsie = std::make_shared<mie_proxy_csr_t>(proc, CSR_VSIE, vsip_vsie_accr);
add_hypervisor_csr(CSR_VSIE, vsie);
auto sie = std::make_shared<virtualized_csr_t>(proc, nonvirtual_sie, vsie);
if (xlen == 32 && proc->extension_enabled_const(EXT_SSAIA)) {
add_hypervisor_csr(CSR_VSIE, std::make_shared<rv32_low_csr_t>(proc, CSR_VSIE, vsie));
add_hypervisor_csr(CSR_VSIEH, std::make_shared<rv32_high_csr_t>(proc, CSR_VSIEH, vsie));
add_supervisor_csr(CSR_SIE, std::make_shared<rv32_low_csr_t>(proc, CSR_SIE, sie));
add_supervisor_csr(CSR_SIEH, std::make_shared<rv32_high_csr_t>(proc, CSR_SIEH, sie));
} else {
add_hypervisor_csr(CSR_VSIE, vsie);
add_supervisor_csr(CSR_SIE, sie);
}
add_hypervisor_csr(CSR_HIE, std::make_shared<mie_proxy_csr_t>(proc, CSR_HIE, hip_hie_accr));
@ -207,7 +217,13 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
add_hypervisor_csr(CSR_HSTATUS, hstatus = std::make_shared<hstatus_csr_t>(proc, CSR_HSTATUS));
add_hypervisor_csr(CSR_HGEIE, std::make_shared<const_csr_t>(proc, CSR_HGEIE, 0));
add_hypervisor_csr(CSR_HGEIP, std::make_shared<const_csr_t>(proc, CSR_HGEIP, 0));
add_hypervisor_csr(CSR_HIDELEG, hideleg = std::make_shared<hideleg_csr_t>(proc, CSR_HIDELEG, mideleg));
hideleg = std::make_shared<hideleg_csr_t>(proc, CSR_HIDELEG, mideleg);
if (xlen == 32 && proc->extension_enabled_const(EXT_SSAIA)) {
add_hypervisor_csr(CSR_HIDELEG, std::make_shared<rv32_low_csr_t>(proc, CSR_HIDELEG, hideleg));
add_hypervisor_csr(CSR_HIDELEGH, std::make_shared<rv32_high_csr_t>(proc, CSR_HIDELEGH, hideleg));
} else {
add_hypervisor_csr(CSR_HIDELEG, hideleg);
}
const reg_t hedeleg_mask =
(1 << CAUSE_MISALIGNED_FETCH) |
(1 << CAUSE_FETCH_ACCESS) |

Write Preview
Loading…
Cancel
Save