vadc/vsbc: allow v0 overlap if LMUL = 1

The spec says, "For vadc and vsbc, an illegal instruction exception is raised if the destination vector register is v0 and LMUL > 1." cc @chihminchao @HanKuanChen
6 years ago · a562fdb3aa
1 changed files with 2 additions and 2 deletions
--- a/riscv/decode.h
+++ b/riscv/decode.h
@ -1318,7 +1318,7 @@ VI_LOOP_END
  VI_LOOP_END

 #define VI_VV_LOOP_WITH_CARRY(BODY) \
-  require(insn.rd() != 0); \
+  require(P.VU.vlmul == 1 || insn.rd() != 0); \
  VI_CHECK_SSS(true); \
  VI_GENERAL_LOOP_BASE \
  VI_MASK_VARS \
@ -1338,7 +1338,7 @@ VI_LOOP_END
  VI_LOOP_END

 #define VI_XI_LOOP_WITH_CARRY(BODY) \
-  require(insn.rd() != 0); \
+  require(P.VU.vlmul == 1 || insn.rd() != 0); \
  VI_CHECK_SSS(false); \
  VI_GENERAL_LOOP_BASE \
  VI_MASK_VARS \