triggers: refactor: add take_trigger_action() to processor.h/processor.cc

riscv/execute.cc

@@ -312,18 +312,7 @@ void processor_t::step(size_t n)
         delete mmu->matched_trigger;
         mmu->matched_trigger = NULL;
       }
-      switch (t.action) {
-        case triggers::ACTION_DEBUG_MODE:
-          enter_debug_mode(DCSR_CAUSE_HWBP);
-          break;
-        case triggers::ACTION_DEBUG_EXCEPTION: {
-          trap_breakpoint trap(state.v, t.address);
-          take_trap(trap, pc);
-          break;
-        }
-        default:
-          abort();
-      }
+      take_trigger_action(t.action, t.address, pc);
     }
     catch(trap_debug_mode&)
     {

riscv/processor.cc

@@ -921,6 +921,22 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   }
 }
 
+void processor_t::take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc)
+{
+  switch (action) {
+    case triggers::ACTION_DEBUG_MODE:
+      enter_debug_mode(DCSR_CAUSE_HWBP);
+      break;
+    case triggers::ACTION_DEBUG_EXCEPTION: {
+      trap_breakpoint trap(state.v, breakpoint_tval);
+      take_trap(trap, epc);
+      break;
+    }
+    default:
+      abort();
+  }
+}
+
 void processor_t::disasm(insn_t insn)
 {
   uint64_t bits = insn.bits();

riscv/processor.h

@@ -353,6 +353,7 @@ private:
   void take_pending_interrupt() { take_interrupt(state.mip->read() & state.mie->read()); }
   void take_interrupt(reg_t mask); // take first enabled interrupt in mask
   void take_trap(trap_t& t, reg_t epc); // take an exception
+  void take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc);
   void disasm(insn_t insn); // disassemble and print an instruction
   int paddr_bits();