rvv fix 2021-08-09 (#768)

* rvv: vmadc/vmsbc have been separated into carry and no-carry versions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvv: rename file name by opcode name change

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/insns/vmadc_vi.h

@@ -0,0 +1,2 @@
+// vmadc.vi vd, vs2, simm5
+#include "vmadc_vim.h"

riscv/insns/vmadc_vim.h

@@ -1,4 +1,4 @@
-// vmadc.vim vd, vs2, simm5
+// vmadc.vim vd, vs2, simm5, v0
 VI_XI_LOOP_CARRY
 ({
   auto v0 = P.VU.elt<uint64_t>(0, midx);

riscv/insns/vmadc_vv.h

@@ -0,0 +1,2 @@
+// vmadc.vvm vd, vs2, rs1
+#include "vmadc_vvm.h"

riscv/insns/vmadc_vvm.h

@@ -1,4 +1,4 @@
-// vmadc.vvm vd, vs2, rs1
+// vmadc.vvm vd, vs2, rs1, v0
 VI_VV_LOOP_CARRY
 ({
   auto v0 = P.VU.elt<uint64_t>(0, midx);

riscv/insns/vmadc_vx.h

@@ -0,0 +1,2 @@
+// vadc.vx vd, vs2, rs1
+#include "vmadc_vxm.h"

riscv/insns/vmadc_vxm.h

@@ -1,4 +1,4 @@
-// vadc.vx vd, vs2, rs1
+// vadc.vx vd, vs2, rs1, v0
 VI_XI_LOOP_CARRY
 ({
   auto v0 = P.VU.elt<uint64_t>(0, midx);

riscv/insns/vmsbc_vv.h

@@ -0,0 +1,2 @@
+// vmsbc.vv vd, vs2, rs1
+#include "vmsbc_vvm.h"

riscv/insns/vmsbc_vvm.h

@@ -1,4 +1,4 @@
-// vmsbc.vvm vd, vs2, rs1
+// vmsbc.vvm vd, vs2, rs1, v0
 VI_VV_LOOP_CARRY
 ({
   auto v0 = P.VU.elt<uint64_t>(0, midx);

riscv/insns/vmsbc_vx.h

@@ -0,0 +1,2 @@
+// vmsbc.vx vd, vs2, rs1
+#include "vmsbc_vxm.h"

riscv/insns/vmsbc_vxm.h

@@ -1,4 +1,4 @@
-// vmsbc.vxm vd, vs2, rs1
+// vmsbc.vxm vd, vs2, rs1, v0
 VI_XI_LOOP_CARRY
 ({
   auto &v0 = P.VU.elt<uint64_t>(0, midx);

riscv/riscv.mk.in

@@ -480,6 +480,7 @@ riscv_insn_ext_v_alu_int = \
 	vasub_vx \
 	vasubu_vx \
 	vcompress_vm \
+	vcpop_m \
 	vdiv_vv \
 	vdiv_vx \
 	vdivu_vv \
@@ -488,6 +489,9 @@ riscv_insn_ext_v_alu_int = \
 	viota_m \
 	vmacc_vv \
 	vmacc_vx \
+	vmadc_vv \
+	vmadc_vx \
+	vmadc_vi \
 	vmadc_vim \
 	vmadc_vvm \
 	vmadc_vxm \
@@ -511,7 +515,8 @@ riscv_insn_ext_v_alu_int = \
 	vmnor_mm \
 	vmor_mm \
 	vmornot_mm \
-	vpopc_m \
+	vmsbc_vv \
+	vmsbc_vx \
 	vmsbc_vvm \
 	vmsbc_vxm \
 	vmsbf_m \
@@ -721,7 +726,7 @@ riscv_insn_ext_v_alu_fp = \
 	vfredmax_vs \
 	vfredmin_vs \
 	vfredosum_vs \
-	vfredsum_vs \
+	vfredusum_vs \
 	vfrec7_v \
 	vfrsub_vf \
 	vfrsqrt7_v \
@@ -758,7 +763,7 @@ riscv_insn_ext_v_alu_fp = \
 	vfwnmsac_vf \
 	vfwnmsac_vv \
 	vfwredosum_vs \
-	vfwredsum_vs \
+	vfwredusum_vs \
 	vfwsub_vf \
 	vfwsub_vv \
 	vfwsub_wf \
@@ -813,7 +818,7 @@ riscv_insn_ext_v_amo = \
 	vamoxorei64_v \
 
 riscv_insn_ext_v_ldst = \
-	vle1_v \
+	vlm_v \
 	vle8_v \
 	vle16_v \
 	vle32_v \
@@ -850,7 +855,7 @@ riscv_insn_ext_v_ldst = \
 	vl2re64_v \
 	vl4re64_v \
 	vl8re64_v \
-	vse1_v \
+	vsm_v \
 	vse8_v \
 	vse16_v \
 	vse32_v \