trigger_operation_t -> triggers::operation_t

riscv/mmu.cc

@@ -155,7 +155,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate
 
   if (!matched_trigger) {
     reg_t data = reg_from_bytes(len, bytes);
-    matched_trigger = trigger_exception(OPERATION_LOAD, addr, data);
+    matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, data);
     if (matched_trigger)
       throw *matched_trigger;
   }
@@ -167,7 +167,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_
 
   if (!matched_trigger) {
     reg_t data = reg_from_bytes(len, bytes);
-    matched_trigger = trigger_exception(OPERATION_STORE, addr, data);
+    matched_trigger = trigger_exception(triggers::OPERATION_STORE, addr, data);
     if (matched_trigger)
       throw *matched_trigger;
   }

riscv/mmu.h

@@ -11,6 +11,7 @@
 #include "processor.h"
 #include "memtracer.h"
 #include "byteorder.h"
+#include "triggers.h"
 #include <stdlib.h>
 #include <vector>
 
@@ -41,11 +42,11 @@ class trigger_matched_t
 {
   public:
     trigger_matched_t(int index,
-        trigger_operation_t operation, reg_t address, reg_t data) :
+        triggers::operation_t operation, reg_t address, reg_t data) :
       index(index), operation(operation), address(address), data(data) {}
 
     int index;
-    trigger_operation_t operation;
+    triggers::operation_t operation;
     reg_t address;
     reg_t data;
 };
@@ -111,7 +112,7 @@ public:
       if ((xlate_flags) == 0 && unlikely(tlb_load_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { \
         type##_t data = from_target(*(target_endian<type##_t>*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr)); \
         if (!matched_trigger) { \
-          matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); \
+          matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, data); \
           if (matched_trigger) \
             throw *matched_trigger; \
         } \
@@ -170,7 +171,7 @@ public:
       } \
       else if ((xlate_flags) == 0 && unlikely(tlb_store_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { \
         if (!matched_trigger) { \
-          matched_trigger = trigger_exception(OPERATION_STORE, addr, val); \
+          matched_trigger = trigger_exception(triggers::OPERATION_STORE, addr, val); \
           if (matched_trigger) \
             throw *matched_trigger; \
         } \
@@ -469,9 +470,9 @@ private:
     }
     if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) {
       target_endian<uint16_t>* ptr = (target_endian<uint16_t>*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr);
-      int match = proc->trigger_match(OPERATION_EXECUTE, addr, from_target(*ptr));
+      int match = proc->trigger_match(triggers::OPERATION_EXECUTE, addr, from_target(*ptr));
       if (match >= 0) {
-        throw trigger_matched_t(match, OPERATION_EXECUTE, addr, from_target(*ptr));
+        throw trigger_matched_t(match, triggers::OPERATION_EXECUTE, addr, from_target(*ptr));
       }
     }
     return result;
@@ -481,7 +482,7 @@ private:
     return (uint16_t*)(translate_insn_addr(addr).host_offset + addr);
   }
 
-  inline trigger_matched_t *trigger_exception(trigger_operation_t operation,
+  inline trigger_matched_t *trigger_exception(triggers::operation_t operation,
       reg_t address, reg_t data)
   {
     if (!proc) {

riscv/processor.h

@@ -15,6 +15,7 @@
 #include "entropy_source.h"
 #include "csrs.h"
 #include "isa_parser.h"
+#include "triggers.h"
 
 class processor_t;
 class mmu_t;
@@ -355,7 +356,7 @@ public:
   } halt_request;
 
   // Return the index of a trigger that matched, or -1.
-  inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
+  inline int trigger_match(triggers::operation_t operation, reg_t address, reg_t data)
   {
     if (state.debug_mode)
       return -1;
@@ -368,9 +369,9 @@ public:
         continue;
       }
 
-      if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
-          (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
-          (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
+      if ((operation == triggers::OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
+          (operation == triggers::OPERATION_STORE && !state.mcontrol[i].store) ||
+          (operation == triggers::OPERATION_LOAD && !state.mcontrol[i].load) ||
           (state.prv == PRV_M && !state.mcontrol[i].m) ||
           (state.prv == PRV_S && !state.mcontrol[i].s) ||
           (state.prv == PRV_U && !state.mcontrol[i].u)) {

riscv/triggers.h

@@ -2,6 +2,13 @@
 #define _RISCV_TRIGGERS_H
 
 namespace triggers {
+
+typedef enum {
+  OPERATION_EXECUTE,
+  OPERATION_STORE,
+  OPERATION_LOAD,
+} operation_t;
+
 };
 
 #endif