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riscv-isa-sim
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rvv: add float conversion for rtz variants 

new features in spec 0.9
ref:
  https://github.com/riscv/riscv-v-spec/issues/352

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/448/head
Chih-Min Chao 6 years ago
parent
2dd63195c0
commit
a261be3dc6
9 changed files with 87 additions and 1 deletions
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  1. 18
      riscv/encoding.h
  2. 8
      riscv/insns/vfcvt_rtz_x_f_v.h
  3. 8
      riscv/insns/vfcvt_rtz_xu_f_v.h
  4. 10
      riscv/insns/vfncvt_rtz_x_f_w.h
  5. 10
      riscv/insns/vfncvt_rtz_xu_f_w.h
  6. 10
      riscv/insns/vfwcvt_rtz_x_f_v.h
  7. 10
      riscv/insns/vfwcvt_rtz_xu_f_v.h
  8. 6
      riscv/riscv.mk.in
  9. 8
      spike_main/disasm.cc

18
riscv/encoding.h
View File

@ -1052,6 +1052,10 @@
#define MASK_VFCVT_F_XU_V 0xfc0ff07f
#define MATCH_VFCVT_F_X_V 0x88019057
#define MASK_VFCVT_F_X_V 0xfc0ff07f
#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057
#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f
#define MATCH_VFCVT_RTZ_X_F_V 0x88039057
#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f
#define MATCH_VFWCVT_XU_F_V 0x88041057
#define MASK_VFWCVT_XU_F_V 0xfc0ff07f
#define MATCH_VFWCVT_X_F_V 0x88049057
@ -1062,6 +1066,10 @@
#define MASK_VFWCVT_F_X_V 0xfc0ff07f
#define MATCH_VFWCVT_F_F_V 0x88061057
#define MASK_VFWCVT_F_F_V 0xfc0ff07f
#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057
#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f
#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057
#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f
#define MATCH_VFNCVT_XU_F_W 0x88081057
#define MASK_VFNCVT_XU_F_W 0xfc0ff07f
#define MATCH_VFNCVT_X_F_W 0x88089057
@ -1074,6 +1082,10 @@
#define MASK_VFNCVT_F_F_W 0xfc0ff07f
#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057
#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f
#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057
#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f
#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057
#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f
#define MATCH_VFSQRT_V 0x8c001057
#define MASK_VFSQRT_V 0xfc0ff07f
#define MATCH_VFCLASS_V 0x8c081057
@ -2257,17 +2269,23 @@ DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V)
DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V)
DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V)
DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V)
DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V)
DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V)
DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V)
DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V)
DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V)
DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V)
DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V)
DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V)
DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W)
DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W)
DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W)
DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)

8
riscv/insns/vfcvt_rtz_x_f_v.h
View File

@ -0,0 +1,8 @@
// vfcvt.x.f.v vd, vd2, vm
VI_VFP_VF_LOOP
({
P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true);
},
{
P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true);
})

8
riscv/insns/vfcvt_rtz_xu_f_v.h
View File

@ -0,0 +1,8 @@
// vfcvt.xu.f.v vd, vd2, vm
VI_VFP_VF_LOOP
({
P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true);
},
{
P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true);
})

10
riscv/insns/vfncvt_rtz_x_f_w.h
View File

@ -0,0 +1,10 @@
// vfncvt.x.f.v vd, vs2, vm
VI_CHECK_SDS(false);
if (P.VU.vsew == e32)
require(p->supports_extension('D'));
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true);
set_fp_exceptions;
VI_VFP_LOOP_END

10
riscv/insns/vfncvt_rtz_xu_f_w.h
View File

@ -0,0 +1,10 @@
// vfncvt.xu.f.v vd, vs2, vm
VI_CHECK_SDS(false);
if (P.VU.vsew == e32)
require(p->supports_extension('D'));
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, softfloat_round_minMag, true);
set_fp_exceptions;
VI_VFP_LOOP_END

10
riscv/insns/vfwcvt_rtz_x_f_v.h
View File

@ -0,0 +1,10 @@
// vfwcvt.x.f.v vd, vs2, vm
VI_CHECK_DSS(false);
if (P.VU.vsew == e32)
require(p->supports_extension('D'));
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, softfloat_round_minMag, true);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

10
riscv/insns/vfwcvt_rtz_xu_f_v.h
View File

@ -0,0 +1,10 @@
// vfwcvt.xu.f.v vd, vs2, vm
VI_CHECK_DSS(false);
if (P.VU.vsew == e32)
require(p->supports_extension('D'));
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, softfloat_round_minMag, true);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

6
riscv/riscv.mk.in
View File

@ -511,6 +511,8 @@ riscv_insn_ext_v_alu_fp = \
vfclass_v \
vfcvt_f_x_v \
vfcvt_f_xu_v \
vfcvt_rtz_x_f_v \
vfcvt_rtz_xu_f_v \
vfcvt_x_f_v \
vfcvt_xu_f_v \
vfdiv_vf \
@ -538,6 +540,8 @@ riscv_insn_ext_v_alu_fp = \
vfncvt_f_x_w \
vfncvt_f_xu_w \
vfncvt_rod_f_f_w \
vfncvt_rtz_x_f_w \
vfncvt_rtz_xu_f_w \
vfncvt_x_f_w \
vfncvt_xu_f_w \
vfnmacc_vf \
@ -570,6 +574,8 @@ riscv_insn_ext_v_alu_fp = \
vfwcvt_f_f_v \
vfwcvt_f_x_v \
vfwcvt_f_xu_v \
vfwcvt_rtz_x_f_v \
vfwcvt_rtz_xu_f_v \
vfwcvt_x_f_v \
vfwcvt_xu_f_v \
vfwmacc_vf \

8
spike_main/disasm.cc
View File

@ -1055,9 +1055,15 @@ disassembler_t::disassembler_t(int xlen)
add_insn(new disasm_insn_t(#name "cvt.f.x." #suf, \
match_##name##cvt_f_x_##suf, mask_##name##cvt_f_x_##suf, \
{&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.rtz.xu.f." #suf, \
match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
add_insn(new disasm_insn_t(#name "cvt.rtz.x.f." #suf, \
match_##name##cvt_x_f_##suf, mask_##name##cvt_x_f_##suf, \
{&vd, &vs2, &opt, &vm})); \
//OPFVV/OPFVF
//0b01_0000
//0b00_0000
DISASM_OPIV_VF_INSN(vfadd);
DISASM_OPIV_S__INSN(vfredsum);
DISASM_OPIV_VF_INSN(vfsub);

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