From 05ccf3289afb2087db356778dea1731dd97f7cea Mon Sep 17 00:00:00 2001
From: Sergei Zimmerman <sergei.zimmerman@syntacore.com>
Date: Mon, 10 Nov 2025 19:41:27 +0300
Subject: [PATCH 1/2] Gate Zaamo,Zalrsc instructions behind corresponding
 extensions, not MISA A

This is already done for the disassembler (disasm/disasm.cc:882),
but the actual implementations haven't been updated.

A already implies Zaamo,Zalrsc and the other way around (both enabled imply A).
Makes the implementation slightly more correct for when only one standard
extensions is enabled out of the two.
---
 riscv/insns/amoadd_d.h  | 2 +-
 riscv/insns/amoadd_w.h  | 2 +-
 riscv/insns/amoand_d.h  | 2 +-
 riscv/insns/amoand_w.h  | 2 +-
 riscv/insns/amomax_d.h  | 2 +-
 riscv/insns/amomax_w.h  | 2 +-
 riscv/insns/amomaxu_d.h | 2 +-
 riscv/insns/amomaxu_w.h | 2 +-
 riscv/insns/amomin_d.h  | 2 +-
 riscv/insns/amomin_w.h  | 2 +-
 riscv/insns/amominu_d.h | 2 +-
 riscv/insns/amominu_w.h | 2 +-
 riscv/insns/amoor_d.h   | 2 +-
 riscv/insns/amoor_w.h   | 2 +-
 riscv/insns/amoswap_d.h | 2 +-
 riscv/insns/amoswap_w.h | 2 +-
 riscv/insns/amoxor_d.h  | 2 +-
 riscv/insns/amoxor_w.h  | 2 +-
 riscv/insns/lr_d.h      | 2 +-
 riscv/insns/lr_w.h      | 2 +-
 riscv/insns/sc_d.h      | 2 +-
 riscv/insns/sc_w.h      | 2 +-
 22 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index 8573aa50..f9ccd89a 100644
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs + RS2; }));
diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index c288b3bc..8f1265be 100644
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs + RS2; })));
diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index 2df7ce2a..e44cd21a 100644
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs & RS2; }));
diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 962165f1..05ff2db4 100644
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs & RS2; })));
diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index ab95da09..7445fe38 100644
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); }));
diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index 132c2e04..a2b65fdd 100644
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); })));
diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index e2371aa0..32c6d95e 100644
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); }));
diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index ebbdd415..030ce30f 100644
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); })));
diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index 419e42e6..97f5173a 100644
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); }));
diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index 749149c7..266f5746 100644
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); })));
diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index b4bab475..9f67295a 100644
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); }));
diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index 680eef27..34475d70 100644
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); })));
diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index c201d88a..0b255d30 100644
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs | RS2; }));
diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index 0adac5b7..6dc2e338 100644
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs | RS2; })));
diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index 62a95b0a..2fb13980 100644
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t UNUSED lhs) { return RS2; }));
diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index 819579cd..3ca75131 100644
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t UNUSED lhs) { return RS2; })));
diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h
index a40050fd..4f257df3 100644
--- a/riscv/insns/amoxor_d.h
+++ b/riscv/insns/amoxor_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs ^ RS2; }));
diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h
index af025d68..6eb7a20e 100644
--- a/riscv/insns/amoxor_w.h
+++ b/riscv/insns/amoxor_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZAAMO);
 WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs ^ RS2; })));
diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 214daff2..32a16e5a 100644
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,3 +1,3 @@
-require_extension('A');
+require_extension(EXT_ZALRSC);
 require_rv64;
 WRITE_RD(MMU.load_reserved<int64_t>(RS1));
diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 354590f2..fb0005c6 100644
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1,2 +1,2 @@
-require_extension('A');
+require_extension(EXT_ZALRSC);
 WRITE_RD(MMU.load_reserved<int32_t>(RS1));
diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index ac82c3ec..1b6880b6 100644
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,4 +1,4 @@
-require_extension('A');
+require_extension(EXT_ZALRSC);
 require_rv64;
 
 bool have_reservation = MMU.store_conditional<uint64_t>(RS1, RS2);
diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 48fea4b5..6df6a679 100644
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,4 +1,4 @@
-require_extension('A');
+require_extension(EXT_ZALRSC);
 
 bool have_reservation = MMU.store_conditional<uint32_t>(RS1, RS2);
 

From 0e4af9d92d5b55c2281f94d9a20e26f41e283cca Mon Sep 17 00:00:00 2001
From: Sergei Zimmerman <sergei.zimmerman@syntacore.com>
Date: Tue, 11 Nov 2025 12:44:14 +0300
Subject: [PATCH 2/2] Gate AMO from Zicfiss behind EXT_ZAAMO

Same as the previous commit, but for Zicfiss. Can't
find the exact details in Unprivileged spec version 20251030,
but that must be a spec oversight. QEMU implements it the same
way e.g.
---
 riscv/insns/ssamoswap_d.h | 2 +-
 riscv/insns/ssamoswap_w.h | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/riscv/insns/ssamoswap_d.h b/riscv/insns/ssamoswap_d.h
index 10ea5eff..4169ac3e 100644
--- a/riscv/insns/ssamoswap_d.h
+++ b/riscv/insns/ssamoswap_d.h
@@ -1,5 +1,5 @@
 require_extension(EXT_ZICFISS);
-require_extension('A');
+require_extension(EXT_ZAAMO);
 require_rv64;
 
 DECLARE_XENVCFG_VARS(SSE);
diff --git a/riscv/insns/ssamoswap_w.h b/riscv/insns/ssamoswap_w.h
index 3cdefc79..d971ebec 100644
--- a/riscv/insns/ssamoswap_w.h
+++ b/riscv/insns/ssamoswap_w.h
@@ -1,7 +1,6 @@
 require_extension(EXT_ZICFISS);
-require_extension('A');
+require_extension(EXT_ZAAMO);
 
 DECLARE_XENVCFG_VARS(SSE);
 require_envcfg(SSE);
 WRITE_RD(sext32(MMU.ssamoswap<uint32_t>(RS1, RS2)));
-