new tohost/fromhost semantics

riscv/htif.cc

@@ -116,17 +116,19 @@ int htif_t::wait_for_packet()
           sim->mmu->store_uint64((p.addr+i)*HTIF_DATA_ALIGN, p.data[i]);
         break;
       case APP_CMD_READ_CONTROL_REG:
+      case APP_CMD_WRITE_CONTROL_REG:
       {
         assert(pcr_coreid < sim->num_cores());
         assert(p.data_size == 1);
         ackpacket.data_size = 1;
         reg_t pcr = sim->procs[pcr_coreid]->get_pcr(pcr_reg);
+        if (pcr_reg == PCR_TOHOST)
+          sim->procs[pcr_coreid]->tohost = 0;
         memcpy(ackpacket.data, &pcr, sizeof(pcr));
-        break;
-      }
-      case APP_CMD_WRITE_CONTROL_REG:
-        assert(pcr_coreid < sim->num_cores());
-        assert(p.data_size == 1);
+
+        if (p.cmd == APP_CMD_READ_CONTROL_REG)
+          break;
+
         if (pcr_reg == PCR_RESET)
         {
           reset = p.data[0] & 1;
@@ -139,6 +141,7 @@ int htif_t::wait_for_packet()
           sim->procs[pcr_coreid]->set_pcr(pcr_reg, pcr);
         }
         break;
+      }
     }
 
     send_packet(&ackpacket);

riscv/insns/mtpcr.h

@@ -1,5 +1,4 @@
 require_supervisor;
 reg_t val = get_pcr(insn.rtype.rs1);
-if (val == 0 || insn.rtype.rs1 != PCR_TOHOST)
-  set_pcr(insn.rtype.rs1, RS2);
+set_pcr(insn.rtype.rs1, RS2);
 RD = val;

riscv/processor.cc

@@ -271,7 +271,8 @@ void processor_t::set_pcr(int which, reg_t val)
       vecbanks_count = __builtin_popcountll(vecbanks);
       break;
     case PCR_TOHOST:
-      tohost = val;
+      if (tohost == 0)
+        tohost = val;
       break;
     case PCR_FROMHOST:
       fromhost = val;

riscv/processor.h

@@ -87,6 +87,7 @@ private:
 
   friend class sim_t;
   friend class mmu_t;
+  friend class htif_t;
 
   #include "dispatch.h"
 };