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@ -1064,6 +1064,12 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) |
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throw trap_illegal_instruction(insn.bits()); |
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} |
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const insn_desc_t insn_desc_t::illegal_instruction = { |
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0, 0, |
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&::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, |
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&::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction |
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}; |
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reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc) |
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{ |
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// The illegal instruction can be longer than ILEN bits, where the tval will
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@ -1072,51 +1078,30 @@ reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc) |
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throw trap_illegal_instruction(insn.bits() & 0xffffffffULL); |
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} |
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static insn_desc_t |
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propagate_instruction_in_vector(std::vector<insn_desc_t> &instructions, |
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std::vector<insn_desc_t>::iterator it) { |
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assert(it != instructions.end()); |
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insn_desc_t desc = *it; |
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if (it->mask != 0 && it != instructions.begin() && |
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std::next(it) != instructions.end()) { |
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if (it->match != std::prev(it)->match && |
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it->match != std::next(it)->match) { |
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// move to front of opcode list to reduce miss penalty
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while (--it >= instructions.begin()) |
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*std::next(it) = *it; |
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instructions[0] = desc; |
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} |
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} |
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return desc; |
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} |
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insn_func_t processor_t::decode_insn(insn_t insn) |
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{ |
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// look up opcode in hash table
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size_t idx = insn.bits() % OPCODE_CACHE_SIZE; |
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insn_desc_t desc = opcode_cache[idx]; |
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auto [hit, desc] = opcode_cache[idx].lookup(insn.bits()); |
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bool rve = extension_enabled('E'); |
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if (unlikely(insn.bits() != desc.match)) { |
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if (unlikely(!hit)) { |
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// fall back to linear search
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auto matching = [insn_bits = insn.bits()](const insn_desc_t &d) { |
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return (insn_bits & d.mask) == d.match; |
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}; |
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auto p = std::find_if(custom_instructions.begin(), |
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custom_instructions.end(), matching); |
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if (p != custom_instructions.end()) { |
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desc = propagate_instruction_in_vector(custom_instructions, p); |
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} else { |
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if (p == custom_instructions.end()) { |
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p = std::find_if(instructions.begin(), instructions.end(), matching); |
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assert(p != instructions.end()); |
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desc = propagate_instruction_in_vector(instructions, p); |
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} |
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opcode_cache[idx] = desc; |
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opcode_cache[idx].match = insn.bits(); |
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desc = &*p; |
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opcode_cache[idx].replace(insn.bits(), desc); |
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} |
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return desc.func(xlen, rve, log_commits_enabled); |
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return desc->func(xlen, rve, log_commits_enabled); |
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} |
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void processor_t::register_insn(insn_desc_t desc, bool is_custom) { |
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@ -1131,19 +1116,8 @@ void processor_t::register_insn(insn_desc_t desc, bool is_custom) { |
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void processor_t::build_opcode_map() |
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{ |
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struct cmp { |
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bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) { |
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if (lhs.match == rhs.match) |
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return lhs.mask > rhs.mask; |
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return lhs.match > rhs.match; |
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} |
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}; |
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std::sort(instructions.begin(), instructions.end(), cmp()); |
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std::sort(custom_instructions.begin(), custom_instructions.end(), cmp()); |
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for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) |
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opcode_cache[i] = insn_desc_t::illegal(); |
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opcode_cache[i].reset(); |
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} |
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void processor_t::register_extension(extension_t *x) { |
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@ -1165,15 +1139,12 @@ void processor_t::register_base_instructions() |
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{ |
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#define DECLARE_INSN(name, match, mask) \ |
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insn_bits_t name##_match = (match), name##_mask = (mask); \ |
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bool name##_supported = true; |
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isa_extension_t name##_ext = NUM_ISA_EXTENSIONS; \ |
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bool name##_overlapping = false; |
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#include "encoding.h" |
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#undef DECLARE_INSN |
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#define DECLARE_OVERLAP_INSN(name, ext) { name##_supported = isa->extension_enabled(ext); } |
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#include "overlap_list.h" |
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#undef DECLARE_OVERLAP_INSN |
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#define DEFINE_INSN(name) \ |
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extern reg_t fast_rv32i_##name(processor_t*, insn_t, reg_t); \ |
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extern reg_t fast_rv64i_##name(processor_t*, insn_t, reg_t); \ |
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@ -1182,8 +1153,14 @@ void processor_t::register_base_instructions() |
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extern reg_t logged_rv32i_##name(processor_t*, insn_t, reg_t); \ |
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extern reg_t logged_rv64i_##name(processor_t*, insn_t, reg_t); \ |
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extern reg_t logged_rv32e_##name(processor_t*, insn_t, reg_t); \ |
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extern reg_t logged_rv64e_##name(processor_t*, insn_t, reg_t); \ |
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if (name##_supported) { \ |
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extern reg_t logged_rv64e_##name(processor_t*, insn_t, reg_t); |
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#include "insn_list.h" |
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#undef DEFINE_INSN |
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// add overlapping instructions first, in order
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#define DECLARE_OVERLAP_INSN(name, ext) \ |
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name##_overlapping = true; \ |
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if (isa->extension_enabled(ext)) \ |
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register_base_insn((insn_desc_t) { \ |
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name##_match, \ |
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name##_mask, \ |
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@ -1194,11 +1171,31 @@ void processor_t::register_base_instructions() |
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logged_rv32i_##name, \ |
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logged_rv64i_##name, \ |
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logged_rv32e_##name, \ |
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logged_rv64e_##name}); \ |
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} |
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logged_rv64e_##name}); |
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#include "overlap_list.h" |
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#undef DECLARE_OVERLAP_INSN |
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// add all other instructions. since they are non-overlapping, the order
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// does not affect correctness, but more frequent instructions should
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// appear earlier to improve search time on opcode_cache misses.
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#define DEFINE_INSN(name) \ |
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if (!name##_overlapping) \ |
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register_base_insn((insn_desc_t) { \ |
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name##_match, \ |
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name##_mask, \ |
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fast_rv32i_##name, \ |
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fast_rv64i_##name, \ |
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fast_rv32e_##name, \ |
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fast_rv64e_##name, \ |
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logged_rv32i_##name, \ |
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logged_rv64i_##name, \ |
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logged_rv32e_##name, \ |
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logged_rv64e_##name}); |
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#include "insn_list.h" |
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#undef DEFINE_INSN |
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// terminate instruction list with a catch-all
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register_base_insn(insn_desc_t::illegal()); |
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register_base_insn(insn_desc_t::illegal_instruction); |
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build_opcode_map(); |
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} |
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Andrew Waterman
2 years ago
GitHub