Merge pull request #655 from chihminchao/rvv-v0.10

Rvv v0.10

README.md

@@ -20,7 +20,7 @@ Spike supports the following RISC-V ISA features:
   - C extension, v2.0
   - B extension, v0.92
   - K extension, v0.8.1 ([Scalar Cryptography](https://github.com/riscv/riscv-crypto))
-  - V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (_requires a 64-bit host_)
+  - V extension, v0.10, w/ Zvlsseg/Zvamo (_requires a 64-bit host_)
   - Bi-endianness
   - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
   - Machine, Supervisor, and User modes, v1.11

disasm/disasm.cc

@@ -800,6 +800,7 @@ disassembler_t::disassembler_t(int xlen)
   DISASM_INSN("c.fsd", c_fsd, 0, {&rvc_fp_rs2s, &rvc_ld_address});
   DISASM_INSN("c.fsdsp", c_fsdsp, 0, {&rvc_fp_rs2, &rvc_sdsp_address});
 
+  DISASM_INSN("vsetivli", vsetivli, 0, {&xrd, &zimm5, &v_vtype});
   DISASM_INSN("vsetvli", vsetvli, 0, {&xrd, &xrs1, &v_vtype});
   DISASM_INSN("vsetvl", vsetvl, 0, {&xrd, &xrs1, &xrs2});
 
@@ -808,10 +809,6 @@ disassembler_t::disassembler_t(int xlen)
     add_insn(new disasm_insn_t(#name "16"   #ff ".v",  match_##name##16##ff##_v,    mask_##name##16##ff##_v   | mask_nf, fmt)); \
     add_insn(new disasm_insn_t(#name "32"   #ff ".v",  match_##name##32##ff##_v,    mask_##name##32##ff##_v   | mask_nf, fmt)); \
     add_insn(new disasm_insn_t(#name "64"   #ff ".v",  match_##name##64##ff##_v,    mask_##name##64##ff##_v   | mask_nf, fmt)); \
-    add_insn(new disasm_insn_t(#name "128"  #ff ".v",  match_##name##128##ff##_v,   mask_##name##128##ff##_v  | mask_nf, fmt)); \
-    add_insn(new disasm_insn_t(#name "256"  #ff ".v",  match_##name##256##ff##_v,   mask_##name##256##ff##_v  | mask_nf, fmt)); \
-    add_insn(new disasm_insn_t(#name "512"  #ff ".v",  match_##name##512##ff##_v,   mask_##name##512##ff##_v  | mask_nf, fmt)); \
-    add_insn(new disasm_insn_t(#name "1024" #ff ".v",  match_##name##1024##ff##_v,  mask_##name##1024##ff##_v | mask_nf, fmt)); \
 
   std::vector<const arg_t *> v_ld_unit = {&vd, &v_address, &opt, &vm};
   std::vector<const arg_t *> v_st_unit = {&vs3, &v_address, &opt, &vm};
@@ -820,6 +817,9 @@ disassembler_t::disassembler_t(int xlen)
   std::vector<const arg_t *> v_ld_index = {&vd, &v_address, &vs2, &opt, &vm};
   std::vector<const arg_t *> v_st_index = {&vs3, &v_address, &vs2, &opt, &vm};
 
+  add_insn(new disasm_insn_t("vle1.v",  match_vle1_v,     mask_vle1_v, v_ld_unit));
+  add_insn(new disasm_insn_t("vse1.v",  match_vse1_v,     mask_vse1_v, v_st_unit));
+
   DISASM_VMEM_INSN(vle,    v_ld_unit,   );
   DISASM_VMEM_INSN(vluxei, v_ld_index,  );
   DISASM_VMEM_INSN(vlse,   v_ld_stride, );
@@ -1244,8 +1244,8 @@ disassembler_t::disassembler_t(int xlen)
 
   //vfunary1
   DISASM_INSN("vfsqrt.v", vfsqrt_v, 0, {&vd, &vs2, &opt, &vm});
-  DISASM_INSN("vfrsqrte7.v", vfrsqrte7_v, 0, {&vd, &vs2, &opt, &vm});
-  DISASM_INSN("vfrece7.v", vfrece7_v, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vfrsqrt7.v", vfrsqrt7_v, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vfrec7.v", vfrec7_v, 0, {&vd, &vs2, &opt, &vm});
   DISASM_INSN("vfclass.v", vfclass_v, 0, {&vd, &vs2, &opt, &vm});
 
   DISASM_OPIV_VF_INSN(vfmul);

riscv/decode.h

@@ -119,6 +119,7 @@ public:
   uint64_t v_nf() { return x(29, 3); }
   uint64_t v_simm5() { return xs(15, 5); }
   uint64_t v_zimm5() { return x(15, 5); }
+  uint64_t v_zimm10() { return x(20, 10); }
   uint64_t v_zimm11() { return x(20, 11); }
   uint64_t v_lmul() { return x(20, 2); }
   uint64_t v_frac_lmul() { return x(22, 1); }
@@ -531,18 +532,18 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
     } \
   }
 
-#define VI_CHECK_STORE(elt_width) \
+#define VI_CHECK_STORE(elt_width, is_mask_ldst) \
   require_vector(false); \
-  reg_t veew = sizeof(elt_width##_t) * 8; \
-  float vemul = ((float)veew / P.VU.vsew * P.VU.vflmul); \
+  reg_t veew = is_mask_ldst ? 1 : sizeof(elt_width##_t) * 8; \
+  float vemul = is_mask_ldst ? 1 : ((float)veew / P.VU.vsew * P.VU.vflmul); \
   reg_t emul = vemul < 1 ? 1 : vemul; \
   require(vemul >= 0.125 && vemul <= 8); \
   require_align(insn.rd(), vemul); \
   require((nf * emul) <= (NVPR / 4) && \
           (insn.rd() + nf * emul) <= NVPR); \
 
-#define VI_CHECK_LOAD(elt_width) \
-  VI_CHECK_STORE(elt_width); \
+#define VI_CHECK_LOAD(elt_width, is_mask_ldst) \
+  VI_CHECK_STORE(elt_width, is_mask_ldst); \
   require_vm; \
 
 #define VI_CHECK_DSS(is_vs1) \
@@ -1606,12 +1607,12 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   } \
 }
 
-#define VI_LD(stride, offset, elt_width) \
+#define VI_LD(stride, offset, elt_width, is_mask_ldst) \
   const reg_t nf = insn.v_nf() + 1; \
-  const reg_t vl = P.VU.vl; \
+  const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \
   const reg_t baseAddr = RS1; \
   const reg_t vd = insn.rd(); \
-  VI_CHECK_LOAD(elt_width); \
+  VI_CHECK_LOAD(elt_width, is_mask_ldst); \
   for (reg_t i = 0; i < vl; ++i) { \
     VI_ELEMENT_SKIP(i); \
     VI_STRIP(i); \
@@ -1660,12 +1661,12 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   } \
   P.VU.vstart = 0;
 
-#define VI_ST(stride, offset, elt_width) \
+#define VI_ST(stride, offset, elt_width, is_mask_ldst) \
   const reg_t nf = insn.v_nf() + 1; \
-  const reg_t vl = P.VU.vl; \
+  const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \
   const reg_t baseAddr = RS1; \
   const reg_t vs3 = insn.rd(); \
-  VI_CHECK_STORE(elt_width); \
+  VI_CHECK_STORE(elt_width, is_mask_ldst); \
   for (reg_t i = 0; i < vl; ++i) { \
     VI_STRIP(i) \
     VI_ELEMENT_SKIP(i); \
@@ -1720,7 +1721,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   const reg_t vl = p->VU.vl; \
   const reg_t baseAddr = RS1; \
   const reg_t rd_num = insn.rd(); \
-  VI_CHECK_LOAD(elt_width); \
+  VI_CHECK_LOAD(elt_width, false); \
   bool early_stop = false; \
   for (reg_t i = p->VU.vstart; i < vl; ++i) { \
     VI_STRIP(i); \

riscv/encoding.h

@@ -1,6 +1,6 @@
 /*
  * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in
- * https://github.com/riscv/riscv-opcodes (c4d2cc0)
+ * https://github.com/riscv/riscv-opcodes (e8f0392)
  */
 
 /* See LICENSE for license details. */
@@ -1222,10 +1222,16 @@
 #define MASK_CUSTOM3_RD_RS1  0x707f
 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define MATCH_VSETIVLI 0xc0007057
+#define MASK_VSETIVLI  0xc000707f
 #define MATCH_VSETVLI 0x7057
 #define MASK_VSETVLI  0x8000707f
 #define MATCH_VSETVL 0x80007057
 #define MASK_VSETVL  0xfe00707f
+#define MATCH_VLE1_V 0x2b00007
+#define MASK_VLE1_V  0xfff0707f
+#define MATCH_VSE1_V 0x2b00027
+#define MASK_VSE1_V  0xfff0707f
 #define MATCH_VLE8_V 0x7
 #define MASK_VLE8_V  0x1df0707f
 #define MATCH_VLE16_V 0x5007
@@ -1584,10 +1590,10 @@
 #define MASK_VFNCVT_RTZ_X_F_W  0xfc0ff07f
 #define MATCH_VFSQRT_V 0x4c001057
 #define MASK_VFSQRT_V  0xfc0ff07f
-#define MATCH_VFRSQRTE7_V 0x4c021057
-#define MASK_VFRSQRTE7_V  0xfc0ff07f
-#define MATCH_VFRECE7_V 0x4c029057
-#define MASK_VFRECE7_V  0xfc0ff07f
+#define MATCH_VFRSQRT7_V 0x4c021057
+#define MASK_VFRSQRT7_V  0xfc0ff07f
+#define MATCH_VFREC7_V 0x4c029057
+#define MASK_VFREC7_V  0xfc0ff07f
 #define MATCH_VFCLASS_V 0x4c081057
 #define MASK_VFCLASS_V  0xfc0ff07f
 #define MATCH_VFWADD_VV 0xc0001057
@@ -2887,8 +2893,11 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI)
 DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI)
 DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
+DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V)
+DECLARE_INSN(vse1_v, MATCH_VSE1_V, MASK_VSE1_V)
 DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V)
 DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V)
 DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V)
@@ -3068,8 +3077,8 @@ DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
 DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
 DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
 DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
-DECLARE_INSN(vfrsqrte7_v, MATCH_VFRSQRTE7_V, MASK_VFRSQRTE7_V)
-DECLARE_INSN(vfrece7_v, MATCH_VFRECE7_V, MASK_VFRECE7_V)
+DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V)
+DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V)
 DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
 DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)
 DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS)

riscv/insns/vle16_v.h

@@ -1,2 +1,2 @@
 // vle16.v and vlseg[2-8]e16.v
-VI_LD(0, (i * nf + fn), int16);
+VI_LD(0, (i * nf + fn), int16, false);

riscv/insns/vle1_v.h

@@ -0,0 +1,2 @@
+// vle1.v and vlseg[2-8]e8.v
+VI_LD(0, (i * nf + fn), int8, true);

riscv/insns/vle32_v.h

@@ -1,2 +1,2 @@
 // vle32.v and vlseg[2-8]e32.v
-VI_LD(0, (i * nf + fn), int32);
+VI_LD(0, (i * nf + fn), int32, false);

riscv/insns/vle64_v.h

@@ -1,2 +1,2 @@
 // vle64.v and vlseg[2-8]e64.v
-VI_LD(0, (i * nf + fn), int64);
+VI_LD(0, (i * nf + fn), int64, false);

riscv/insns/vle8_v.h

@@ -1,2 +1,2 @@
 // vle8.v and vlseg[2-8]e8.v
-VI_LD(0, (i * nf + fn), int8);
+VI_LD(0, (i * nf + fn), int8, false);

riscv/insns/vlse16_v.h

@@ -1,2 +1,2 @@
 // vlse16.v and vlsseg[2-8]e16.v
-VI_LD(i * RS2, fn, int16);
+VI_LD(i * RS2, fn, int16, false);

riscv/insns/vlse32_v.h

@@ -1,2 +1,2 @@
 // vlse32.v and vlsseg[2-8]e32.v
-VI_LD(i * RS2, fn, int32);
+VI_LD(i * RS2, fn, int32, false);

riscv/insns/vlse64_v.h

@@ -1,2 +1,2 @@
 // vlse64.v and vlsseg[2-8]e64.v
-VI_LD(i * RS2, fn, int64);
+VI_LD(i * RS2, fn, int64, false);

riscv/insns/vlse8_v.h

@@ -1,2 +1,2 @@
 // vlse8.v and vlsseg[2-8]e8.v
-VI_LD(i * RS2, fn, int8);
+VI_LD(i * RS2, fn, int8, false);

riscv/insns/vse16_v.h

@@ -1,2 +1,2 @@
 // vse16.v and vsseg[2-8]e16.v
-VI_ST(0, (i * nf + fn), uint16);
+VI_ST(0, (i * nf + fn), uint16, false);

riscv/insns/vse1_v.h

@@ -0,0 +1,2 @@
+// vse1.v
+VI_ST(0, (i * nf + fn), uint8, true);

riscv/insns/vse32_v.h

@@ -1,2 +1,2 @@
 // vse32.v and vsseg[2-8]e32.v
-VI_ST(0, (i * nf + fn), uint32);
+VI_ST(0, (i * nf + fn), uint32, false);

riscv/insns/vse64_v.h

@@ -1,2 +1,2 @@
 // vse64.v and vsseg[2-8]e64.v
-VI_ST(0, (i * nf + fn), uint64);
+VI_ST(0, (i * nf + fn), uint64, false);

riscv/insns/vse8_v.h

@@ -1,2 +1,2 @@
 // vse8.v and vsseg[2-8]e8.v
-VI_ST(0, (i * nf + fn), uint8);
+VI_ST(0, (i * nf + fn), uint8, false);

riscv/insns/vsetivli.h

@@ -0,0 +1,2 @@
+require_vector_novtype(false, false);
+WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10()));

riscv/insns/vsse16_v.h

@@ -1,2 +1,2 @@
 // vsse16v and vssseg[2-8]e16.v
-VI_ST(i * RS2, fn, uint16);
+VI_ST(i * RS2, fn, uint16, false);

riscv/insns/vsse32_v.h

@@ -1,2 +1,2 @@
 // vsse32.v and vssseg[2-8]e32.v
-VI_ST(i * RS2, fn, uint32);
+VI_ST(i * RS2, fn, uint32, false);

riscv/insns/vsse64_v.h

@@ -1,2 +1,2 @@
 // vsse64.v and vssseg[2-8]e64.v
-VI_ST(i * RS2, fn, uint64);
+VI_ST(i * RS2, fn, uint64, false);

riscv/insns/vsse8_v.h

@@ -1,2 +1,2 @@
 // vsse8.v and vssseg[2-8]e8.v
-VI_ST(i * RS2, fn, uint8);
+VI_ST(i * RS2, fn, uint8, false);

riscv/processor.cc

@@ -393,11 +393,9 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
     vlmax = (VLEN/vsew) * vflmul;
     vta = extract64(newType, 6, 1);
     vma = extract64(newType, 7, 1);
-    vediv = 1 << extract64(newType, 8, 2);
 
     vill = !(vflmul >= 0.125 && vflmul <= 8)
            || vsew > std::min(vflmul, 1.0f) * ELEN
-           || vediv != 1
            || (newType >> 8) != 0;
 
     if (vill) {

riscv/processor.h

@@ -244,7 +244,6 @@ typedef enum {
 typedef enum {
   // 65('A') ~ 90('Z') is reserved for standard isa in misa
   EXT_ZFH   = 0,
-  EXT_ZVEDIV,
 } isa_extension_t;
 
 typedef enum {
@@ -491,7 +490,7 @@ public:
       reg_t vlmax;
       reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
       reg_t vma, vta;
-      reg_t vediv, vsew;
+      reg_t vsew;
       float vflmul;
       reg_t ELEN, VLEN;
       bool vill;

riscv/riscv.mk.in

@@ -724,9 +724,9 @@ riscv_insn_ext_v_alu_fp = \
 	vfredmin_vs \
 	vfredosum_vs \
 	vfredsum_vs \
-	vfrece7_v \
+	vfrec7_v \
 	vfrsub_vf \
-	vfrsqrte7_v \
+	vfrsqrt7_v \
 	vfsgnj_vf \
 	vfsgnj_vv \
 	vfsgnjn_vf \
@@ -815,6 +815,7 @@ riscv_insn_ext_v_amo = \
 	vamoxorei64_v \
 
 riscv_insn_ext_v_ldst = \
+	vle1_v \
 	vle8_v \
 	vle16_v \
 	vle32_v \
@@ -851,6 +852,7 @@ riscv_insn_ext_v_ldst = \
 	vl2re64_v \
 	vl4re64_v \
 	vl8re64_v \
+	vse1_v \
 	vse8_v \
 	vse16_v \
 	vse32_v \
@@ -873,6 +875,7 @@ riscv_insn_ext_v_ldst = \
 	vs8r_v \
 
 riscv_insn_ext_v_ctrl = \
+	vsetivli \
 	vsetvli \
 	vsetvl \