Merge pull request #1920 from riscv-software-src/zvqdotq

Add Zvqdotq extension

disasm/disasm.cc

@@ -1844,6 +1844,13 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
     DISASM_OPIV_MULTIPLYADD__X__INSN(vwmaccus,  1);
     DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccsu,  0);
 
+    if (ext_enabled(EXT_ZVQDOTQ)) {
+      DISASM_OPIV_VX__INSN(vqdot,   0);
+      DISASM_OPIV_VX__INSN(vqdotu,  0);
+      DISASM_OPIV_VX__INSN(vqdotsu, 0);
+      DISASM_OPIV__X__INSN(vqdotus, 0);
+    }
+
     #undef DISASM_OPIV_VXI_INSN
     #undef DISASM_OPIV_VX__INSN
     #undef DISASM_OPIV__XI_INSN

disasm/isa_parser.cc

@@ -317,6 +317,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZVKSED] = true;
     } else if (ext_str == "zvksh") {
       extension_table[EXT_ZVKSH] = true;
+    } else if (ext_str == "zvqdotq") {
+      extension_table[EXT_ZVQDOTQ] = true;
     } else if (ext_str == "zvkt") {
     } else if (ext_str == "sstc") {
         extension_table[EXT_SSTC] = true;

riscv/encoding.h

@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (47862ce)
+ * https://github.com/riscv/riscv-opcodes (8899b32)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -81,8 +81,9 @@
 #define USTATUS_UPIE        0x00000010
 
 #define MNSTATUS_NMIE       0x00000008
-#define MNSTATUS_MNPP       0x00001800
 #define MNSTATUS_MNPV       0x00000080
+#define MNSTATUS_MNPELP     0x00000200
+#define MNSTATUS_MNPP       0x00001800
 
 #define DCSR_XDEBUGVER      (15U<<28)
 #define DCSR_EXTCAUSE       (7<<24)
@@ -181,11 +182,13 @@
 #define MENVCFG_CBZE  0x00000080
 #define MENVCFG_PMM   0x0000000300000000
 #define MENVCFG_DTE   0x0800000000000000
+#define MENVCFG_CDE   0x1000000000000000
 #define MENVCFG_ADUE  0x2000000000000000
 #define MENVCFG_PBMTE 0x4000000000000000
 #define MENVCFG_STCE  0x8000000000000000
 
 #define MENVCFGH_DTE   0x08000000
+#define MENVCFGH_CDE   0x10000000
 #define MENVCFGH_ADUE  0x20000000
 #define MENVCFGH_PBMTE 0x40000000
 #define MENVCFGH_STCE  0x80000000
@@ -194,6 +197,7 @@
 #define MSTATEEN0_FCSR     0x00000002
 #define MSTATEEN0_JVT      0x00000004
 #define MSTATEEN0_CTR      0x0040000000000000
+#define MSTATEEN0_PRIV113  0x0100000000000000
 #define MSTATEEN0_PRIV114  0x0080000000000000
 #define MSTATEEN0_HCONTEXT 0x0200000000000000
 #define MSTATEEN0_AIA      0x0800000000000000
@@ -202,6 +206,7 @@
 #define MSTATEEN_HSTATEEN  0x8000000000000000
 
 #define MSTATEEN0H_CTR      0x00400000
+#define MSTATEEN0H_PRIV113  0x01000000
 #define MSTATEEN0H_PRIV114  0x00800000
 #define MSTATEEN0H_HCONTEXT 0x02000000
 #define MSTATEEN0H_AIA      0x08000000
@@ -2140,6 +2145,20 @@
 #define MASK_VOR_VV 0xfc00707f
 #define MATCH_VOR_VX 0x28004057
 #define MASK_VOR_VX 0xfc00707f
+#define MATCH_VQDOT_VV 0xb0002057
+#define MASK_VQDOT_VV 0xfc00707f
+#define MATCH_VQDOT_VX 0xb0006057
+#define MASK_VQDOT_VX 0xfc00707f
+#define MATCH_VQDOTSU_VV 0xa8002057
+#define MASK_VQDOTSU_VV 0xfc00707f
+#define MATCH_VQDOTSU_VX 0xa8006057
+#define MASK_VQDOTSU_VX 0xfc00707f
+#define MATCH_VQDOTU_VV 0xa0002057
+#define MASK_VQDOTU_VV 0xfc00707f
+#define MATCH_VQDOTU_VX 0xa0006057
+#define MASK_VQDOTU_VX 0xfc00707f
+#define MATCH_VQDOTUS_VX 0xb8006057
+#define MASK_VQDOTUS_VX 0xfc00707f
 #define MATCH_VREDAND_VS 0x4002057
 #define MASK_VREDAND_VS 0xfc00707f
 #define MATCH_VREDMAX_VS 0x1c002057
@@ -2768,6 +2787,7 @@
 #define CSR_VSIEH 0x214
 #define CSR_VSIPH 0x254
 #define CSR_VSTIMECMPH 0x25d
+#define CSR_HEDELEGH 0x612
 #define CSR_HTIMEDELTAH 0x615
 #define CSR_HIDELEGH 0x613
 #define CSR_HVIENH 0x618
@@ -3830,6 +3850,13 @@ DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
 DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI)
 DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
 DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX)
+DECLARE_INSN(vqdot_vv, MATCH_VQDOT_VV, MASK_VQDOT_VV)
+DECLARE_INSN(vqdot_vx, MATCH_VQDOT_VX, MASK_VQDOT_VX)
+DECLARE_INSN(vqdotsu_vv, MATCH_VQDOTSU_VV, MASK_VQDOTSU_VV)
+DECLARE_INSN(vqdotsu_vx, MATCH_VQDOTSU_VX, MASK_VQDOTSU_VX)
+DECLARE_INSN(vqdotu_vv, MATCH_VQDOTU_VV, MASK_VQDOTU_VV)
+DECLARE_INSN(vqdotu_vx, MATCH_VQDOTU_VX, MASK_VQDOTU_VX)
+DECLARE_INSN(vqdotus_vx, MATCH_VQDOTUS_VX, MASK_VQDOTUS_VX)
 DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)
 DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS)
 DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS)
@@ -4313,6 +4340,7 @@ DECLARE_CSR(stimecmph, CSR_STIMECMPH)
 DECLARE_CSR(vsieh, CSR_VSIEH)
 DECLARE_CSR(vsiph, CSR_VSIPH)
 DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH)
+DECLARE_CSR(hedelegh, CSR_HEDELEGH)
 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
 DECLARE_CSR(hidelegh, CSR_HIDELEGH)
 DECLARE_CSR(hvienh, CSR_HVIENH)

riscv/insns/vqdot_common.h

@@ -0,0 +1,15 @@
+#define UNPACK_32_TO_8(IN, TYPE, OUT_ARR) \
+    int64_t OUT_ARR[4]; \
+    OUT_ARR[0] = (TYPE)((IN) & 0xff); \
+    OUT_ARR[1] = (TYPE)((IN >> 8) & 0xff); \
+    OUT_ARR[2] = (TYPE)((IN >> 16) & 0xff); \
+    OUT_ARR[3] = (TYPE)((IN >> 24) & 0xff); \
+
+#define VQDOT(IN1, IN2, TYPE1, TYPE2) \
+    UNPACK_32_TO_8(IN1, TYPE1, unpacked_vs1) \
+    UNPACK_32_TO_8(IN2, TYPE2, unpacked_vs2) \
+    uint64_t result = unpacked_vs1[0]*unpacked_vs2[0] + \
+                     unpacked_vs1[1]*unpacked_vs2[1] + \
+                     unpacked_vs1[2]*unpacked_vs2[2] + \
+                     unpacked_vs1[3]*unpacked_vs2[3] \
+

riscv/insns/vqdot_vv.h

@@ -0,0 +1,11 @@
+// vqdot.vv vd, vs2, vs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VV_LOOP
+({
+  VQDOT(vs1, vs2, int8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/insns/vqdot_vx.h

@@ -0,0 +1,11 @@
+// vqdot.vx vd, vs2, rs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP
+({
+  VQDOT(rs1, vs2, int8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/insns/vqdotsu_vv.h

@@ -0,0 +1,11 @@
+// vqdotsu.vv vd, vs2, vs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VV_LOOP
+({
+  VQDOT(vs1, vs2, uint8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/insns/vqdotsu_vx.h

@@ -0,0 +1,11 @@
+// vqdotsu.vx vd, vs2, rs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP
+({
+  VQDOT(rs1, vs2, uint8_t, int8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/insns/vqdotu_vv.h

@@ -0,0 +1,11 @@
+// vqdotu.vv vd, vs2, vs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VV_LOOP
+({
+  VQDOT(vs1, vs2, uint8_t, uint8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/insns/vqdotu_vx.h

@@ -0,0 +1,11 @@
+// vqdotu.vx vd, vs2, rs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP
+({
+  VQDOT(rs1, vs2, uint8_t, uint8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/insns/vqdotus_vx.h

@@ -0,0 +1,11 @@
+// vqdotus.vx vd, vs2, rs1, vm
+#include "vqdot_common.h"
+
+require_extension(EXT_ZVQDOTQ);
+require(P.VU.vsew == e32);
+
+VI_VX_LOOP
+({
+  VQDOT(rs1, vs2, int8_t, uint8_t);
+  vd = (vd + result) & 0xffffffff;
+})

riscv/isa_parser.h

@@ -65,6 +65,7 @@ typedef enum {
   EXT_ZVKNHB,
   EXT_ZVKSED,
   EXT_ZVKSH,
+  EXT_ZVQDOTQ,
   EXT_SSTC,
   EXT_ZAAMO,
   EXT_ZALRSC,

riscv/riscv.mk.in

@@ -860,11 +860,21 @@ riscv_insn_ext_v_ctrl = \
 	vsetvli \
 	vsetvl \
 
+riscv_insn_ext_zvqdotq = \
+	vqdot_vv \
+	vqdot_vx \
+	vqdotu_vv \
+	vqdotu_vx \
+	vqdotsu_vv \
+	vqdotsu_vx \
+	vqdotus_vx \
+
 riscv_insn_ext_v = \
 	$(riscv_insn_ext_v_alu_fp) \
 	$(riscv_insn_ext_v_alu_int) \
 	$(riscv_insn_ext_v_ctrl) \
 	$(riscv_insn_ext_v_ldst) \
+	$(riscv_insn_ext_zvqdotq) \
 
 riscv_insn_ext_h = \
 	hfence_gvma \