[sim] removed undefined behavior for non-canonical inputs

riscv/decode.h

@@ -199,10 +199,12 @@ private:
                              softfloat_exceptionFlags = 0; })
 
 #define require_rvc if(!(sr & SR_EC)) throw trap_illegal_instruction
+#define insn_length(x) (((x).bits & 0x3) < 0x3 ? 2 : 4)
 
 #define sext32(x) ((sreg_t)(int32_t)(x))
-#define insn_length(x) (((x).bits & 0x3) < 0x3 ? 2 : 4)
+#define zext32(x) ((reg_t)(uint32_t)(x))
 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
+#define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
 
 // RVC stuff
 

riscv/insns/div.h

@@ -3,4 +3,4 @@ if(RS2 == 0)
 else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = RS1;
 else
-  RD = sext_xprlen(sreg_t(RS1) / sreg_t(RS2));
+  RD = sext_xprlen(sext_xprlen(RS1) / sext_xprlen(RS2));

riscv/insns/divu.h

@@ -1,4 +1,4 @@
 if(RS2 == 0)
   RD = UINT64_MAX;
 else
-  RD = sext_xprlen(RS1 / RS2);
+  RD = sext_xprlen(zext_xprlen(RS1) / zext_xprlen(RS2));

riscv/insns/divuw.h

@@ -2,4 +2,4 @@ require_xpr64;
 if(RS2 == 0)
   RD = UINT64_MAX;
 else
-  RD = sext32(RS1 / RS2);
+  RD = sext32(zext32(RS1) / zext32(RS2));

riscv/insns/divw.h

@@ -6,4 +6,4 @@ if(RS2 == 0)
 else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = RS1;
 else
-  RD = sext32(sreg_t(RS1) / sreg_t(RS2));
+  RD = sext32(int32_t(RS1) / int32_t(RS2));

riscv/insns/mulh.h

@@ -5,4 +5,4 @@ if(xpr64)
   RD = (int128_t(a) * int128_t(b)) >> 64;
 }
 else
-  RD = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
+  RD = sext32((sext32(RS1) * sext32(RS2)) >> 32);

riscv/insns/mulhsu.h

@@ -5,4 +5,4 @@ if(xpr64)
   RD = (int128_t(a) * uint128_t(b)) >> 64;
 }
 else
-  RD = sext32((sreg_t(RS1) * reg_t((uint32_t)RS2)) >> 32);
+  RD = sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32);

riscv/insns/rem.h

@@ -3,4 +3,4 @@ if(RS2 == 0)
 else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = 0;
 else
-  RD = sext_xprlen(sreg_t(RS1) % sreg_t(RS2));
+  RD = sext_xprlen(sext_xprlen(RS1) % sext_xprlen(RS2));

riscv/insns/remu.h

@@ -1,4 +1,4 @@
 if(RS2 == 0)
   RD = RS1;
 else
-  RD = sext_xprlen(RS1 % RS2);
+  RD = sext_xprlen(zext_xprlen(RS1) % zext_xprlen(RS2));

riscv/insns/remuw.h

@@ -2,4 +2,4 @@ require_xpr64;
 if(RS2 == 0)
   RD = RS1;
 else
-  RD = sext32(RS1 % RS2);
+  RD = sext32(zext_xprlen(RS1) % zext_xprlen(RS2));

riscv/insns/remw.h

@@ -6,4 +6,4 @@ if(RS2 == 0)
 else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
   RD = 0;
 else
-  RD = sext32(sreg_t(RS1) % sreg_t(RS2));
+  RD = sext32(int32_t(RS1) % int32_t(RS2));

riscv/insns/sra.h

@@ -1 +1 @@
-RD = sext_xprlen(sreg_t(RS1) >> (RS2 & (xprlen-1)));
+RD = sext_xprlen(sext_xprlen(RS1) >> (RS2 & (xprlen-1)));

riscv/insns/sraw.h

@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(sreg_t(RS1) >> (RS2 & 0x1F));
+RD = sext32(int32_t(RS1) >> (RS2 & 0x1F));