Zero-extend flw, fmv_s_x instructions

- This makes Spike more consistent with its zero-extending behavior
     regarding other SP operations when placed into the 64b f-registers.

riscv/insns/flw.h

@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));
+WRITE_FRD(MMU.load_uint32(RS1 + insn.i_imm()));

riscv/insns/fmv_s_x.h

@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(RS1);
+WRITE_FRD(zext32(RS1));