From 956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 9 Nov 2020 15:10:41 -0800
Subject: [PATCH] Update readme to reflect bi-endian support

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index 5e4e3bd6..2f2bfddf 100644
--- a/README.md
+++ b/README.md
@@ -20,6 +20,7 @@ Spike supports the following RISC-V ISA features:
   - C extension, v2.0
   - B extension, v0.92
   - V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (_requires a 64-bit host_)
+  - Bi-endianness
   - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
   - Machine, Supervisor, and User modes, v1.11
   - Debug v0.14