DRY in illegal-instruction descriptors

riscv/processor.cc

@@ -1068,7 +1068,7 @@ void processor_t::build_opcode_map()
   std::sort(instructions.begin(), instructions.end(), cmp());
 
   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
-    opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
+    opcode_cache[i] = insn_desc_t::illegal();
 }
 
 void processor_t::register_extension(extension_t* x)
@@ -1107,7 +1107,9 @@ void processor_t::register_base_instructions()
   #include "insn_list.h"
   #undef DEFINE_INSN
 
-  register_insn({0, 0, &illegal_instruction, &illegal_instruction});
+  // terminate instruction list with a catch-all
+  register_insn(insn_desc_t::illegal());
+
   build_opcode_map();
 }
 

riscv/processor.h

@@ -23,6 +23,8 @@ class trap_t;
 class extension_t;
 class disassembler_t;
 
+reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
+
 struct insn_desc_t
 {
   insn_bits_t match;
@@ -31,6 +33,11 @@ struct insn_desc_t
   insn_func_t rv64;
 
   insn_func_t func(int xlen) { return xlen == 64 ? rv64 : rv32; }
+
+  static insn_desc_t illegal()
+  {
+    return {0, 0, &illegal_instruction, &illegal_instruction};
+  }
 };
 
 // regnum, data
@@ -596,8 +603,6 @@ public:
   vectorUnit_t VU;
 };
 
-reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
-
 #define REGISTER_INSN(proc, name, match, mask, archen) \
   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \