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riscv-isa-sim
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commitlog: rvv: add commitlog support to float instrunctions 

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/383/head
Chih-Min Chao 6 years ago
parent
e1cb87f7d7
commit
9413a45196
15 changed files with 30 additions and 31 deletions
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  1. 22
      riscv/decode.h
  2. 5
      riscv/insns/vfmerge_vfm.h
  3. 8
      riscv/insns/vfmv_s_f.h
  4. 4
      riscv/insns/vfmv_v_f.h
  5. 2
      riscv/insns/vfncvt_f_f_w.h
  6. 2
      riscv/insns/vfncvt_f_x_w.h
  7. 2
      riscv/insns/vfncvt_f_xu_w.h
  8. 2
      riscv/insns/vfncvt_rod_f_f_w.h
  9. 2
      riscv/insns/vfncvt_x_f_w.h
  10. 2
      riscv/insns/vfncvt_xu_f_w.h
  11. 2
      riscv/insns/vfwcvt_f_f_v.h
  12. 2
      riscv/insns/vfwcvt_f_x_v.h
  13. 2
      riscv/insns/vfwcvt_f_xu_v.h
  14. 2
      riscv/insns/vfwcvt_x_f_v.h
  15. 2
      riscv/insns/vfwcvt_xu_f_v.h

22
riscv/decode.h
View File

@ -1630,7 +1630,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
float32_t rs1 = f32(READ_FREG(rs1_num)); \
VI_LOOP_ELEMENT_SKIP(); \
uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); \
uint64_t &vdi = P.VU.elt<uint64_t>(rd_num, midx); \
uint64_t &vdi = P.VU.elt<uint64_t>(rd_num, midx, true); \
uint64_t res = 0;
#define VI_VFP_LOOP_REDUCTION_BASE(width) \
@ -1639,7 +1639,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
vd_0 = vs1_0;\
for (reg_t i=P.VU.vstart; i<vl; ++i){ \
VI_LOOP_ELEMENT_SKIP(); \
int##width##_t &vd = P.VU.elt<int##width##_t>(rd_num, i); \
int##width##_t &vd = P.VU.elt<int##width##_t>(rd_num, i, true); \
float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); \
#define VI_VFP_LOOP_WIDE_REDUCTION_BASE \
@ -1661,7 +1661,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
} \
P.VU.vstart = 0; \
if (vl > 0) { \
P.VU.elt<type_sew_t<x>::type>(rd_num, 0) = vd_0.v; \
P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \
}
#define VI_VFP_LOOP_CMP_END \
@ -1685,7 +1685,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
case e32: {\
float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
float32_t vs1 = P.VU.elt<float32_t>(rs1_num, i); \
float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
BODY32; \
@ -1693,7 +1693,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
break; \
}\
case e64: {\
float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
float64_t vs1 = P.VU.elt<float64_t>(rs1_num, i); \
float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
BODY64; \
@ -1745,7 +1745,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
case e32: {\
float32_t &vd = P.VU.elt<float32_t>(rd_num, i); \
float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
float32_t rs1 = f32(READ_FREG(rs1_num)); \
float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
BODY32; \
@ -1753,7 +1753,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
break; \
}\
case e64: {\
float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
float64_t rs1 = f64(READ_FREG(rs1_num)); \
float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
BODY64; \
@ -1801,7 +1801,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
case e32: {\
float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
BODY; \
@ -1823,7 +1823,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
case e32: {\
float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \
BODY; \
@ -1844,7 +1844,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
case e32: {\
float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
BODY; \
@ -1864,7 +1864,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
case e32: {\
float64_t &vd = P.VU.elt<float64_t>(rd_num, i); \
float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \
BODY; \

5
riscv/insns/vfmerge_vfm.h
View File

@ -2,12 +2,11 @@
require(insn.rd() != 0);
VI_CHECK_SSS(false);
VI_VFP_COMMON;
reg_t sew = P.VU.vsew;
switch(P.VU.vsew) {
case 32:
for (reg_t i=P.VU.vstart; i<vl; ++i) {
auto &vd = P.VU.elt<float32_t>(rd_num, i);
auto &vd = P.VU.elt<float32_t>(rd_num, i, true);
auto rs1 = f32(READ_FREG(rs1_num));
auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
@ -20,7 +19,7 @@ switch(P.VU.vsew) {
break;
case 64:
for (reg_t i=P.VU.vstart; i<vl; ++i) {
auto &vd = P.VU.elt<float64_t>(rd_num, i);
auto &vd = P.VU.elt<float64_t>(rd_num, i, true);
auto rs1 = f64(READ_FREG(rs1_num));
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);

8
riscv/insns/vfmv_s_f.h
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@ -11,15 +11,15 @@ if (vl > 0) {
switch(P.VU.vsew) {
case 32:
if (FLEN == 64)
P.VU.elt<uint32_t>(rd_num, 0) = f64(FRS1).v;
P.VU.elt<uint32_t>(rd_num, 0, true) = f64(FRS1).v;
else
P.VU.elt<uint32_t>(rd_num, 0) = f32(FRS1).v;
P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v;
break;
case 64:
if (FLEN == 64)
P.VU.elt<uint64_t>(rd_num, 0) = f64(FRS1).v;
P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v;
else
P.VU.elt<uint64_t>(rd_num, 0) = f32(FRS1).v;
P.VU.elt<uint64_t>(rd_num, 0, true) = f32(FRS1).v;
break;
}
}

4
riscv/insns/vfmv_v_f.h
View File

@ -4,7 +4,7 @@ VI_VFP_COMMON
switch(P.VU.vsew) {
case e32:
for (reg_t i=P.VU.vstart; i<vl; ++i) {
auto &vd = P.VU.elt<float32_t>(rd_num, i);
auto &vd = P.VU.elt<float32_t>(rd_num, i, true);
auto rs1 = f32(READ_FREG(rs1_num));
vd = rs1;
@ -12,7 +12,7 @@ switch(P.VU.vsew) {
break;
case e64:
for (reg_t i=P.VU.vstart; i<vl; ++i) {
auto &vd = P.VU.elt<float64_t>(rd_num, i);
auto &vd = P.VU.elt<float64_t>(rd_num, i, true);
auto rs1 = f64(READ_FREG(rs1_num));
vd = rs1;

2
riscv/insns/vfncvt_f_f_w.h
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@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2);
P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
set_fp_exceptions;
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_f_x_w.h
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@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = i64_to_f32(vs2);
P.VU.elt<float32_t>(rd_num, i, true) = i64_to_f32(vs2);
set_fp_exceptions;
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_f_xu_w.h
View File

@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = ui64_to_f32(vs2);
P.VU.elt<float32_t>(rd_num, i, true) = ui64_to_f32(vs2);
set_fp_exceptions;
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_rod_f_f_w.h
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@ -6,6 +6,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
softfloat_roundingMode = softfloat_round_odd;
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2);
P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
set_fp_exceptions;
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_x_f_w.h
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@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<int32_t>(rd_num, i) = f64_to_i32(vs2, STATE.frm, true);
P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true);
set_fp_exceptions;
VI_VFP_LOOP_END

2
riscv/insns/vfncvt_xu_f_w.h
View File

@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
P.VU.elt<uint32_t>(rd_num, i) = f64_to_ui32(vs2, STATE.frm, true);
P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true);
set_fp_exceptions;
VI_VFP_LOOP_END

2
riscv/insns/vfwcvt_f_f_v.h
View File

@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
P.VU.elt<float64_t>(rd_num, i) = f32_to_f64(vs2);
P.VU.elt<float64_t>(rd_num, i, true) = f32_to_f64(vs2);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

2
riscv/insns/vfwcvt_f_x_v.h
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@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
P.VU.elt<float64_t>(rd_num, i) = i32_to_f64(vs2);
P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

2
riscv/insns/vfwcvt_f_xu_v.h
View File

@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
P.VU.elt<float64_t>(rd_num, i) = ui32_to_f64(vs2);
P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

2
riscv/insns/vfwcvt_x_f_v.h
View File

@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
P.VU.elt<int64_t>(rd_num, i) = f32_to_i64(vs2, STATE.frm, true);
P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

2
riscv/insns/vfwcvt_xu_f_v.h
View File

@ -5,6 +5,6 @@ if (P.VU.vsew == e32)
VI_VFP_LOOP_BASE
auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
P.VU.elt<uint64_t>(rd_num, i) = f32_to_ui64(vs2, STATE.frm, true);
P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true);
set_fp_exceptions;
VI_VFP_LOOP_WIDE_END

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