[sim, xcc] branches now have 2-byte-aligned displacements

This will facilitate 16-bit instructions later on

riscv/decode.h

@@ -28,6 +28,8 @@ const int SHAMT_BITS = 6;
 const int FUNCT_BITS = 3;
 const int FFUNCT_BITS = 5;
 const int BIGIMM_BITS = 20;
+const int BRANCH_ALIGN_BITS = 1;
+const int JUMP_ALIGN_BITS = 1;
 
 #define SR_ET    0x0000000000000001ULL
 #define SR_PS    0x0000000000000004ULL
@@ -129,8 +131,8 @@ union insn_t
 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 #define SHAMT insn.rtype.shamt
 #define TARGET insn.jtype.target
-#define BRANCH_TARGET (npc + (SIMM*sizeof(insn_t)))
+#define BRANCH_TARGET (pc + (SIMM << BRANCH_ALIGN_BITS))
-#define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)*sizeof(insn_t)-1)) + TARGET*sizeof(insn_t))
+#define JUMP_TARGET ((pc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction

riscv/processor.cc

@@ -19,6 +19,8 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   epc = 0;
   badvaddr = 0;
   tid = 0;
+  pcr_k0 = 0;
+  pcr_k1 = 0;
   set_sr(SR_S | (support_64bit ? SR_KX : 0));
   set_fsr(0);