Pass cfg object to processor_t constructor

This reduces boilerplate as we add additional options.

riscv/processor.cc

@@ -28,11 +28,10 @@
 #undef STATE
 #define STATE state
 
-processor_t::processor_t(const isa_parser_t *isa, const char* varch,
+processor_t::processor_t(const isa_parser_t *isa, const cfg_t *cfg,
                          simif_t* sim, uint32_t id, bool halt_on_reset,
-                         endianness_t endianness,
                          FILE* log_file, std::ostream& sout_)
-  : debug(false), halt_request(HR_NONE), isa(isa), sim(sim), id(id), xlen(0),
+  : debug(false), halt_request(HR_NONE), isa(isa), cfg(cfg), sim(sim), id(id), xlen(0),
   histogram_enabled(false), log_commits_enabled(false),
   log_file(log_file), sout_(sout_.rdbuf()), halt_on_reset(halt_on_reset),
   in_wfi(false),
@@ -48,10 +47,10 @@ processor_t::processor_t(const isa_parser_t *isa, const char* varch,
   }
 #endif
 
-  parse_varch_string(varch);
+  parse_varch_string(cfg->varch());
 
   register_base_instructions();
-  mmu = new mmu_t(sim, endianness, this);
+  mmu = new mmu_t(sim, cfg->endianness, this);
 
   disassembler = new disassembler_t(isa);
   for (auto e : isa->get_extensions())

riscv/processor.h

@@ -179,13 +179,13 @@ struct state_t
 class processor_t : public abstract_device_t
 {
 public:
-  processor_t(const isa_parser_t *isa, const char* varch,
+  processor_t(const isa_parser_t *isa, const cfg_t* cfg,
               simif_t* sim, uint32_t id, bool halt_on_reset,
-              endianness_t endianness,
               FILE *log_file, std::ostream& sout_); // because of command line option --log and -s we need both
   ~processor_t();
 
   const isa_parser_t &get_isa() { return *isa; }
+  const cfg_t &get_cfg() { return *cfg; }
 
   void set_debug(bool value);
   void set_histogram(bool value);
@@ -280,6 +280,7 @@ public:
 
 private:
   const isa_parser_t * const isa;
+  const cfg_t * const cfg;
 
   simif_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu

riscv/sim.cc

@@ -98,8 +98,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
   debug_mmu = new mmu_t(this, cfg->endianness, NULL);
 
   for (size_t i = 0; i < cfg->nprocs(); i++) {
-    procs[i] = new processor_t(&isa, cfg->varch(), this, cfg->hartids()[i], halted,
+    procs[i] = new processor_t(&isa, cfg, this, cfg->hartids()[i], halted,
-                               cfg->endianness, log_file.get(), sout_);
+                               log_file.get(), sout_);
   }
 
   make_dtb();

spike_main/spike-log-parser.cc

@@ -28,8 +28,19 @@ int main(int UNUSED argc, char** argv)
   parser.option(0, "isa", 1, [&](const char* s){isa_string = s;});
   parser.parse(argv);
 
+  cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0),
+            /*default_bootargs=*/nullptr,
+            /*default_isa=*/DEFAULT_ISA,
+            /*default_priv=*/DEFAULT_PRIV,
+            /*default_varch=*/DEFAULT_VARCH,
+            /*default_endianness*/endianness_little,
+            /*default_pmpregions=*/16,
+            /*default_mem_layout=*/std::vector<mem_cfg_t>(),
+            /*default_hartids=*/std::vector<int>(),
+            /*default_real_time_clint=*/false);
+
   isa_parser_t isa(isa_string, DEFAULT_PRIV);
-  processor_t p(&isa, DEFAULT_VARCH, 0, 0, false, endianness_little, nullptr, cerr);
+  processor_t p(&isa, &cfg, 0, 0, false, nullptr, cerr);
   if (extension) {
     p.register_extension(extension());
   }