Add support for new instructions of Zvfbfmin extension

riscv/insns/vfncvtbf16_f_f_w.h

@@ -0,0 +1,5 @@
+// vfncvtbf16.f.f.w vd, vs2, vm
+VI_VFP_NCVT_BF16_TO_FP(
+  { vd = f32_to_bf16(vs2); },           // BODY16
+  { require_extension(EXT_ZVFBFMIN); }  // CHECK16
+)

riscv/insns/vfwcvtbf16_f_f_v.h

@@ -0,0 +1,5 @@
+// vfwcvtbf16.f.f.v vd, vs2, vm
+VI_VFP_WCVT_FP_TO_BF16(
+  { vd = bf16_to_f32(vs2); },           // BODY16
+  { require_extension(EXT_ZVFBFMIN); }  // CHECK16
+)

riscv/riscv.mk.in

@@ -1363,8 +1363,13 @@ riscv_insn_ext_zfbfmin = \
 	fcvt_bf16_s \
 	fcvt_s_bf16 \
 
+riscv_insn_ext_zvfbfmin = \
+	vfncvtbf16_f_f_w \
+	vfwcvtbf16_f_f_v \
+
 riscv_insn_ext_bf16 = \
 	$(riscv_insn_ext_zfbfmin) \
+	$(riscv_insn_ext_zvfbfmin) \
 
 riscv_insn_list = \
 	$(riscv_insn_ext_a) \

riscv/v_ext_macros.h

@@ -1980,6 +1980,17 @@ reg_t index[P.VU.vlmax]; \
       break; \
   }
 
+#define VI_VFP_WCVT_FP_TO_BF16(BODY, CHECK) \
+  VI_CHECK_DSS(false); \
+  switch (P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(16, 32), CHECK, BODY); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
 #define VI_VFP_WCVT_INT_TO_FP(BODY8, BODY16, BODY32, \
                               CHECK8, CHECK16, CHECK32, \
                               sign) \
@@ -2030,6 +2041,17 @@ reg_t index[P.VU.vlmax]; \
       break; \
   }
 
+#define VI_VFP_NCVT_BF16_TO_FP(BODY, CHECK) \
+  VI_CHECK_SDS(false); \
+  switch (P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 16), CHECK, BODY); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
 #define VI_VFP_NCVT_INT_TO_FP(BODY32, BODY64, \
                               CHECK32, CHECK64, \
                               sign) \