diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 8ace1b93..7860ad4f 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -81,7 +81,7 @@ void debug_module_t::reset()
   for (unsigned i = 0; i < sim->nprocs(); i++) {
     processor_t *proc = sim->get_core(i);
     if (proc)
-      proc->halt_request = false;
+      proc->halt_request = proc->HR_NONE;
   }
 
   dmcontrol = {0};
@@ -204,7 +204,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
           if (!hart_state[i].halted &&
               hart_state[i].haltgroup == hart_state[id].haltgroup) {
             processor_t *proc = sim->get_core(i);
-            proc->halt_request = true;
+            proc->halt_request = proc->HR_GROUP;
             // TODO: What if the debugger comes and writes dmcontrol before the
             // halt occurs?
           }
@@ -797,7 +797,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
               }
               processor_t *proc = processor(i);
               if (proc) {
-                proc->halt_request = dmcontrol.haltreq;
+                proc->halt_request = dmcontrol.haltreq ? proc->HR_REGULAR : proc->HR_NONE;
                 if (dmcontrol.haltreq) {
                   D(fprintf(stderr, "halt hart %d\n", i));
                 }
diff --git a/riscv/encoding.h b/riscv/encoding.h
index 584bc272..a5059cf4 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -65,6 +65,7 @@
 #define DCSR_CAUSE_DEBUGINT 3
 #define DCSR_CAUSE_STEP     4
 #define DCSR_CAUSE_HALT     5
+#define DCSR_CAUSE_GROUP    6
 
 #define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
 #define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
diff --git a/riscv/execute.cc b/riscv/execute.cc
index b4ffc4ce..6f484c55 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -196,8 +196,10 @@ bool processor_t::slow_path()
 void processor_t::step(size_t n)
 {
   if (!state.debug_mode) {
-    if (halt_request) {
+    if (halt_request == HR_REGULAR) {
       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
+    } else if (halt_request == HR_GROUP) {
+      enter_debug_mode(DCSR_CAUSE_GROUP);
     } // !!!The halt bit in DCSR is deprecated.
     else if (state.dcsr.halt) {
       enter_debug_mode(DCSR_CAUSE_HALT);
diff --git a/riscv/processor.cc b/riscv/processor.cc
index e9d8eb9c..12119d4e 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -23,7 +23,7 @@
 processor_t::processor_t(const char* isa, const char* priv, const char* varch,
                          simif_t* sim, uint32_t id, bool halt_on_reset,
                          FILE* log_file)
-  : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), xlen(0),
+  : debug(false), halt_request(HR_NONE), sim(sim), ext(NULL), id(id), xlen(0),
   histogram_enabled(false), log_commits_enabled(false),
   log_file(log_file), halt_on_reset(halt_on_reset),
   extension_table(256, false), last_pc(1), executions(1)
diff --git a/riscv/processor.h b/riscv/processor.h
index 7ff79ef2..c2513405 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -305,7 +305,11 @@ public:
   // When true, take the slow simulation path.
   bool slow_path();
   bool halted() { return state.debug_mode; }
-  bool halt_request;
+  enum {
+    HR_NONE,    /* Halt request is inactive. */
+    HR_REGULAR, /* Regular halt request/debug interrupt. */
+    HR_GROUP    /* Halt requested due to halt group. */
+  } halt_request;
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)