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riscv-isa-sim
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Convert vl to csr_t 

Adds commit log events for vl to many vector instructions.
pull/821/head
Scott Johnson 5 years ago
parent
464a7fb56a
commit
88c1bfce90
No known key found for this signature in database GPG Key ID: 61C1F01D3D1410C9
13 changed files with 37 additions and 41 deletions
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  1. 34
      riscv/decode.h
  2. 2
      riscv/execute.cc
  3. 2
      riscv/insns/vcpop_m.h
  4. 2
      riscv/insns/vfirst_m.h
  5. 2
      riscv/insns/vfmv_s_f.h
  6. 4
      riscv/insns/vid_v.h
  7. 2
      riscv/insns/viota_m.h
  8. 2
      riscv/insns/vmsbf_m.h
  9. 2
      riscv/insns/vmsif_m.h
  10. 2
      riscv/insns/vmsof_m.h
  11. 2
      riscv/insns/vmv_s_x.h
  12. 16
      riscv/processor.cc
  13. 6
      riscv/processor.h

34
riscv/decode.h
View File

@ -614,7 +614,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
#define VI_GENERAL_LOOP_BASE \
require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \
require_vector(true);\
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t sew = P.VU.vsew; \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
@ -639,7 +639,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
#define VI_LOOP_CMP_BASE \
require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \
require_vector(true);\
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t sew = P.VU.vsew; \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
@ -658,7 +658,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
#define VI_LOOP_MASK(op) \
require(P.VU.vsew <= e64); \
require_vector(true);\
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
int midx = i / 64; \
int mpos = i % 64; \
@ -949,7 +949,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
// reduction loop - signed
#define VI_LOOP_REDUCTION_BASE(x) \
require(x >= e8 && x <= e64); \
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
@ -980,7 +980,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
// reduction loop - unsgied
#define VI_ULOOP_REDUCTION_BASE(x) \
require(x >= e8 && x <= e64); \
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
@ -1299,7 +1299,7 @@ VI_LOOP_END
// wide reduction loop - signed
#define VI_LOOP_WIDE_REDUCTION_BASE(sew1, sew2) \
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
@ -1327,7 +1327,7 @@ VI_LOOP_END
// wide reduction loop - unsigned
#define VI_ULOOP_WIDE_REDUCTION_BASE(sew1, sew2) \
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
@ -1521,7 +1521,7 @@ VI_LOOP_END
#define VI_DUPLICATE_VREG(reg_num, idx_sew) \
reg_t index[P.VU.vlmax]; \
for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl->read() != 0; ++i) { \
switch(idx_sew) { \
case e8: \
index[i] = P.VU.elt<uint8_t>(reg_num, i); \
@ -1540,7 +1540,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
#define VI_LD(stride, offset, elt_width, is_mask_ldst) \
const reg_t nf = insn.v_nf() + 1; \
const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \
const reg_t vl = is_mask_ldst ? ((P.VU.vl->read() + 7) / 8) : P.VU.vl->read(); \
const reg_t baseAddr = RS1; \
const reg_t vd = insn.rd(); \
VI_CHECK_LOAD(elt_width, is_mask_ldst); \
@ -1558,7 +1558,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
#define VI_LD_INDEX(elt_width, is_seg) \
const reg_t nf = insn.v_nf() + 1; \
const reg_t vl = P.VU.vl; \
const reg_t vl = P.VU.vl->read(); \
const reg_t baseAddr = RS1; \
const reg_t vd = insn.rd(); \
if (!is_seg) \
@ -1594,7 +1594,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
#define VI_ST(stride, offset, elt_width, is_mask_ldst) \
const reg_t nf = insn.v_nf() + 1; \
const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \
const reg_t vl = is_mask_ldst ? ((P.VU.vl->read() + 7) / 8) : P.VU.vl->read(); \
const reg_t baseAddr = RS1; \
const reg_t vs3 = insn.rd(); \
VI_CHECK_STORE(elt_width, is_mask_ldst); \
@ -1612,7 +1612,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
#define VI_ST_INDEX(elt_width, is_seg) \
const reg_t nf = insn.v_nf() + 1; \
const reg_t vl = P.VU.vl; \
const reg_t vl = P.VU.vl->read(); \
const reg_t baseAddr = RS1; \
const reg_t vs3 = insn.rd(); \
if (!is_seg) \
@ -1649,7 +1649,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
#define VI_LDST_FF(elt_width) \
const reg_t nf = insn.v_nf() + 1; \
const reg_t sew = p->VU.vsew; \
const reg_t vl = p->VU.vl; \
const reg_t vl = p->VU.vl->read(); \
const reg_t baseAddr = RS1; \
const reg_t rd_num = insn.rd(); \
VI_CHECK_LOAD(elt_width, false); \
@ -1668,7 +1668,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
throw; /* Only take exception on zeroth element */ \
/* Reduce VL if an exception occurs on a later element */ \
early_stop = true; \
P.VU.vl = i; \
P.VU.vl->write_raw(i); \
break; \
} \
p->VU.elt<elt_width##_t>(rd_num + fn * emul, vreg_inx, true) = val; \
@ -1765,7 +1765,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
} \
} \
VI_DUPLICATE_VREG(insn.rs2(), idx_type); \
const reg_t vl = P.VU.vl; \
const reg_t vl = P.VU.vl->read(); \
const reg_t baseAddr = RS1; \
const reg_t vd = insn.rd(); \
for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \
@ -1848,7 +1848,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
(P.VU.vsew == e64 && p->extension_enabled('D'))); \
require_vector(true);\
require(STATE.frm->read() < 0x5);\
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \
@ -2264,7 +2264,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
(P.VU.vsew == e16 && p->extension_enabled('F')) || \
(P.VU.vsew == e32 && p->extension_enabled('D'))); \
require(STATE.frm->read() < 0x5);\
reg_t vl = P.VU.vl; \
reg_t vl = P.VU.vl->read(); \
reg_t rd_num = insn.rd(); \
reg_t rs1_num = insn.rs1(); \
reg_t rs2_num = insn.rs2(); \

2
riscv/execute.cc
View File

@ -125,7 +125,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn)
p->VU.vsew,
p->VU.vflmul < 1 ? "mf" : "m",
p->VU.vflmul < 1 ? (reg_t)(1 / p->VU.vflmul) : (reg_t)p->VU.vflmul,
p->VU.vl);
p->VU.vl->read());
show_vec = true;
}

2
riscv/insns/vcpop_m.h
View File

@ -1,7 +1,7 @@
// vmpopc rd, vs2, vm
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t sew = P.VU.vsew;
reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();

2
riscv/insns/vfirst_m.h
View File

@ -1,7 +1,7 @@
// vmfirst rd, vs2
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t sew = P.VU.vsew;
reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();

2
riscv/insns/vfmv_s_f.h
View File

@ -6,7 +6,7 @@ require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZFH)) ||
(P.VU.vsew == e64 && p->extension_enabled('D')));
require(STATE.frm->read() < 0x5);
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
if (vl > 0 && P.VU.vstart->read() < vl) {
reg_t rd_num = insn.rd();

4
riscv/insns/vid_v.h
View File

@ -1,7 +1,7 @@
// vmpopc rd, vs2, vm
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t sew = P.VU.vsew;
reg_t rd_num = insn.rd();
reg_t rs1_num = insn.rs1();
@ -9,7 +9,7 @@ reg_t rs2_num = insn.rs2();
require_align(rd_num, P.VU.vflmul);
require_vm;
for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl; ++i) {
for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl->read(); ++i) {
VI_LOOP_ELEMENT_SKIP();
switch (sew) {

2
riscv/insns/viota_m.h
View File

@ -1,7 +1,7 @@
// vmpopc rd, vs2, vm
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
require_vector(true);
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t sew = P.VU.vsew;
reg_t rd_num = insn.rd();
reg_t rs1_num = insn.rs1();

2
riscv/insns/vmsbf_m.h
View File

@ -5,7 +5,7 @@ require(P.VU.vstart->read() == 0);
require_vm;
require(insn.rd() != insn.rs2());
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();

2
riscv/insns/vmsif_m.h
View File

@ -5,7 +5,7 @@ require(P.VU.vstart->read() == 0);
require_vm;
require(insn.rd() != insn.rs2());
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();

2
riscv/insns/vmsof_m.h
View File

@ -5,7 +5,7 @@ require(P.VU.vstart->read() == 0);
require_vm;
require(insn.rd() != insn.rs2());
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
reg_t rd_num = insn.rd();
reg_t rs2_num = insn.rs2();

2
riscv/insns/vmv_s_x.h
View File

@ -2,7 +2,7 @@
require_vector(true);
require(insn.v_vm() == 1);
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
reg_t vl = P.VU.vl;
reg_t vl = P.VU.vl->read();
if (vl > 0 && P.VU.vstart->read() < vl) {
reg_t rd_num = insn.rd();

16
riscv/processor.cc
View File

@ -556,6 +556,7 @@ void processor_t::vectorUnit_t::reset(){
csrmap[CSR_VXSAT] = vxsat = std::make_shared<vector_csr_t>(p, CSR_VXSAT, /*mask*/ 0x1ul);
csrmap[CSR_VSTART] = vstart = std::make_shared<vector_csr_t>(p, CSR_VSTART, /*mask*/ VLEN - 1);
csrmap[CSR_VXRM] = vxrm = std::make_shared<vector_csr_t>(p, CSR_VXRM, /*mask*/ 0x3ul);
csrmap[CSR_VL] = vl = std::make_shared<vector_csr_t>(p, CSR_VL, /*mask*/ 0);
vtype = 0;
set_vl(0, 0, 0, -1); // default to illegal configuration
@ -584,18 +585,18 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
// set vl
if (vlmax == 0) {
vl = 0;
vl->write_raw(0);
} else if (rd == 0 && rs1 == 0) {
vl = vl > vlmax ? vlmax : vl;
vl->write_raw(vl->read() > vlmax ? vlmax : vl->read());
} else if (rd != 0 && rs1 == 0) {
vl = vlmax;
vl->write_raw(vlmax);
} else if (rs1 != 0) {
vl = reqVL > vlmax ? vlmax : reqVL;
vl->write_raw(reqVL > vlmax ? vlmax : reqVL);
}
vstart->write_raw(0);
setvl_count++;
return vl;
return vl->read();
}
void processor_t::set_debug(bool value)
@ -1022,11 +1023,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
if (!extension_enabled('V'))
break;
ret((VU.vxsat->read() << VCSR_VXSAT_SHIFT) | (VU.vxrm->read() << VCSR_VXRM_SHIFT));
case CSR_VL:
require_vector_vs;
if (!extension_enabled('V'))
break;
ret(VU.vl);
case CSR_VTYPE:
require_vector_vs;
if (!extension_enabled('V'))

6
riscv/processor.h
View File

@ -511,8 +511,8 @@ public:
char reg_referenced[NVPR];
int setvl_count;
reg_t vlmax;
reg_t vl, vtype, vlenb;
vector_csr_t_p vxrm, vstart, vxsat;
reg_t vtype, vlenb;
vector_csr_t_p vxrm, vstart, vxsat, vl;
reg_t vma, vta;
reg_t vsew;
float vflmul;
@ -553,12 +553,12 @@ public:
reg_referenced{0},
setvl_count(0),
vlmax(0),
vl(0),
vtype(0),
vlenb(0),
vxrm(0),
vstart(0),
vxsat(0),
vl(0),
vma(0),
vta(0),
vsew(0),

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