From 87bf9900832003ab2001158ca5d34e226e492df2 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Wed, 24 May 2023 15:05:08 -0700 Subject: [PATCH] Move setting of V=0 for HS-mode trap So it's right next to set_privilege() which it will be combined with next. --- riscv/processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index f0e8ebfe..6fffc31f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -836,7 +836,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) set_privilege(PRV_S); } else if (state.prv <= PRV_S && bit < max_xlen && ((hsdeleg >> bit) & 1)) { // Handle the trap in HS-mode - set_virt(false); reg_t vector = (state.nonvirtual_stvec->read() & 1) && interrupt ? 4 * bit : 0; state.pc = (state.nonvirtual_stvec->read() & ~(reg_t)1) + vector; state.nonvirtual_scause->write(t.cause()); @@ -858,6 +857,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) s = set_field(s, HSTATUS_GVA, t.has_gva()); state.hstatus->write(s); } + set_virt(false); set_privilege(PRV_S); } else { // Handle the trap in M-mode