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@ -13,10 +13,11 @@ |
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#include <assert.h> |
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#include <limits.h> |
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#include <stdexcept> |
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#include <algorithm> |
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processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) |
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: sim(_sim), mmu(_mmu), ext(NULL), id(_id), run(false), debug(false), |
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opcode_bits(0) |
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: sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t), |
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id(_id), run(false), debug(false) |
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{ |
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reset(true); |
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mmu->set_processor(this); |
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@ -24,6 +25,7 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) |
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#define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask) |
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#include "encoding.h" |
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#undef DECLARE_INSN |
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build_opcode_map(); |
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} |
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processor_t::~processor_t() |
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@ -35,10 +37,7 @@ void state_t::reset() |
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// the ISA guarantees on boot that the PC is 0x2000 and the the processor
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// is in supervisor mode, and in 64-bit mode, if supported, with traps
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// and virtual memory disabled.
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sr = SR_S; |
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#ifdef RISCV_ENABLE_64BIT |
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sr |= SR_S64; |
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#endif |
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sr = SR_S | SR_S64; |
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pc = 0x2000; |
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// the following state is undefined upon boot-up,
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@ -74,6 +73,8 @@ void processor_t::reset(bool value) |
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run = !value; |
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state.reset(); // reset the core
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set_pcr(CSR_STATUS, state.sr); |
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if (ext) |
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ext->reset(); // reset the extension
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} |
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@ -185,7 +186,7 @@ void processor_t::disasm(insn_t insn) |
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{ |
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// the disassembler is stateless, so we share it
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fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n", |
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id, state.pc, insn.bits(), disassembler.disassemble(insn).c_str()); |
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id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str()); |
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} |
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reg_t processor_t::set_pcr(int which, reg_t val) |
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@ -215,6 +216,7 @@ reg_t processor_t::set_pcr(int which, reg_t val) |
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if (!ext) |
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state.sr &= ~SR_EA; |
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state.sr &= ~SR_ZERO; |
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rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64); |
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mmu->flush_tlb(); |
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break; |
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case CSR_EPC: |
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@ -328,42 +330,64 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) |
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insn_func_t processor_t::decode_insn(insn_t insn) |
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{ |
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bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64); |
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size_t mask = opcode_map.size()-1; |
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insn_desc_t* desc = opcode_map[insn.bits() & mask]; |
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auto key = insn.bits() & ((1L << opcode_bits)-1); |
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for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it) |
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if ((insn.bits() & it->second.mask) == it->second.match) |
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return rv64 ? it->second.rv64 : it->second.rv32; |
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while ((insn.bits() & desc->mask) != desc->match) |
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desc++; |
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return &illegal_instruction; |
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return rv64 ? desc->rv64 : desc->rv32; |
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} |
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void processor_t::register_insn(insn_desc_t desc) |
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{ |
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assert(desc.mask & 1); |
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if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1)) |
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instructions.push_back(desc); |
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} |
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void processor_t::build_opcode_map() |
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{ |
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size_t buckets = -1; |
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for (auto& inst : instructions) |
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while ((inst.mask & buckets) != buckets) |
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buckets /= 2; |
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buckets++; |
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struct cmp { |
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decltype(insn_desc_t::match) mask; |
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cmp(decltype(mask) mask) : mask(mask) {} |
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bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) { |
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if ((lhs.match & mask) != (rhs.match & mask)) |
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return (lhs.match & mask) < (rhs.match & mask); |
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return lhs.match < rhs.match; |
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} |
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}; |
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std::sort(instructions.begin(), instructions.end(), cmp(buckets-1)); |
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opcode_map.resize(buckets); |
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opcode_store.resize(instructions.size() + 1); |
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size_t j = 0; |
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for (size_t b = 0, i = 0; b < buckets; b++) |
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{ |
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unsigned x = 0; |
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while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) && |
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(opcode_bits == 0 || x <= opcode_bits)) |
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x++; |
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opcode_bits = x; |
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decltype(opcode_map) new_map; |
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for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it) |
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new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second)); |
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opcode_map = new_map; |
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opcode_map[b] = &opcode_store[j]; |
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while (i < instructions.size() && b == (instructions[i].match & (buckets-1))) |
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opcode_store[j++] = instructions[i++]; |
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} |
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opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc)); |
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assert(j == opcode_store.size()-1); |
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opcode_store[j].match = opcode_store[j].mask = 0; |
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opcode_store[j].rv32 = &illegal_instruction; |
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opcode_store[j].rv64 = &illegal_instruction; |
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} |
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void processor_t::register_extension(extension_t* x) |
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{ |
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for (auto insn : x->get_instructions()) |
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register_insn(insn); |
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build_opcode_map(); |
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for (auto disasm_insn : x->get_disasms()) |
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disassembler.add_insn(disasm_insn); |
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disassembler->add_insn(disasm_insn); |
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if (ext != NULL) |
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throw std::logic_error("only one extension may be registered"); |
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ext = x; |
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Andrew Waterman
13 years ago