From 7cc6c0a0d72c42ffed8753e89a71289b040ec8fe Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (Eop) Chen" <yueh.ting.chen@gmail.com>
Date: Sat, 27 Nov 2021 19:14:53 +0800
Subject: [PATCH] Simplify single-width averaging add and subtract (#867)

---
 riscv/decode.h          | 104 +++++++++++-----------------------------
 riscv/insns/vaadd_vv.h  |   2 +-
 riscv/insns/vaadd_vx.h  |   2 +-
 riscv/insns/vaaddu_vv.h |   2 +-
 riscv/insns/vaaddu_vx.h |   2 +-
 riscv/insns/vasub_vv.h  |   2 +-
 riscv/insns/vasub_vx.h  |   2 +-
 riscv/insns/vasubu_vv.h |   2 +-
 riscv/insns/vasubu_vx.h |   2 +-
 9 files changed, 36 insertions(+), 84 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index 0ed7f374..2eccce2d 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1427,85 +1427,37 @@ VI_LOOP_END
   VI_LOOP_END
 
 // average loop
-#define VI_VVX_LOOP_AVG(opd, op, is_vs1) \
-VI_CHECK_SSS(is_vs1); \
+#define VI_VV_LOOP_AVG(op) \
 VRM xrm = p->VU.get_vround_mode(); \
-VI_LOOP_BASE \
-  switch(sew) { \
-    case e8: { \
-     VV_PARAMS(e8); \
-     type_sew_t<e8>::type rs1 = RS1; \
-     auto res = (int32_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-    case e16: { \
-     VV_PARAMS(e16); \
-     type_sew_t<e16>::type rs1 = RS1; \
-     auto res = (int32_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-    case e32: { \
-     VV_PARAMS(e32); \
-     type_sew_t<e32>::type rs1 = RS1; \
-     auto res = (int64_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-    default: { \
-     VV_PARAMS(e64); \
-     type_sew_t<e64>::type rs1 = RS1; \
-     auto res = (int128_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-  } \
-VI_LOOP_END
+VI_VV_LOOP({ \
+  uint128_t res = ((uint128_t)vs2) op vs1; \
+  INT_ROUNDING(res, xrm, 1); \
+  vd = res >> 1; \
+})
 
-#define VI_VVX_ULOOP_AVG(opd, op, is_vs1) \
-VI_CHECK_SSS(is_vs1); \
+#define VI_VX_LOOP_AVG(op) \
 VRM xrm = p->VU.get_vround_mode(); \
-VI_LOOP_BASE \
-  switch(sew) { \
-    case e8: { \
-     VV_U_PARAMS(e8); \
-     type_usew_t<e8>::type rs1 = RS1; \
-     auto res = (uint16_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-    case e16: { \
-     VV_U_PARAMS(e16); \
-     type_usew_t<e16>::type rs1 = RS1; \
-     auto res = (uint32_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-    case e32: { \
-     VV_U_PARAMS(e32); \
-     type_usew_t<e32>::type rs1 = RS1; \
-     auto res = (uint64_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-    default: { \
-     VV_U_PARAMS(e64); \
-     type_usew_t<e64>::type rs1 = RS1; \
-     auto res = (uint128_t)vs2 op opd; \
-     INT_ROUNDING(res, xrm, 1); \
-     vd = res >> 1; \
-     break; \
-    } \
-  } \
-VI_LOOP_END
+VI_VX_LOOP({ \
+  uint128_t res = ((uint128_t)vs2) op rs1; \
+  INT_ROUNDING(res, xrm, 1); \
+  vd = res >> 1; \
+})
+
+#define VI_VV_ULOOP_AVG(op) \
+VRM xrm = p->VU.get_vround_mode(); \
+VI_VV_ULOOP({ \
+  uint128_t res = ((uint128_t)vs2) op vs1; \
+  INT_ROUNDING(res, xrm, 1); \
+  vd = res >> 1; \
+})
+
+#define VI_VX_ULOOP_AVG(op) \
+VRM xrm = p->VU.get_vround_mode(); \
+VI_VX_ULOOP({ \
+  uint128_t res = ((uint128_t)vs2) op rs1; \
+  INT_ROUNDING(res, xrm, 1); \
+  vd = res >> 1; \
+})
 
 //
 // vector: load/store helper 
diff --git a/riscv/insns/vaadd_vv.h b/riscv/insns/vaadd_vv.h
index 0a14467f..0e7e39b4 100644
--- a/riscv/insns/vaadd_vv.h
+++ b/riscv/insns/vaadd_vv.h
@@ -1,2 +1,2 @@
 // vaadd.vv vd, vs2, vs1
-VI_VVX_LOOP_AVG(vs1, +, true);
+VI_VV_LOOP_AVG(+);
diff --git a/riscv/insns/vaadd_vx.h b/riscv/insns/vaadd_vx.h
index ae00d8e4..120e63eb 100644
--- a/riscv/insns/vaadd_vx.h
+++ b/riscv/insns/vaadd_vx.h
@@ -1,2 +1,2 @@
 // vaadd.vx vd, vs2, rs1
-VI_VVX_LOOP_AVG(rs1, +, false);
+VI_VX_LOOP_AVG(+);
diff --git a/riscv/insns/vaaddu_vv.h b/riscv/insns/vaaddu_vv.h
index 2f3fe745..7eb7a895 100644
--- a/riscv/insns/vaaddu_vv.h
+++ b/riscv/insns/vaaddu_vv.h
@@ -1,2 +1,2 @@
 // vaaddu.vv vd, vs2, vs1
-VI_VVX_ULOOP_AVG(vs1, +, true);
+VI_VV_ULOOP_AVG(+);
diff --git a/riscv/insns/vaaddu_vx.h b/riscv/insns/vaaddu_vx.h
index 0e9fddcb..325206f9 100644
--- a/riscv/insns/vaaddu_vx.h
+++ b/riscv/insns/vaaddu_vx.h
@@ -1,2 +1,2 @@
 // vaaddu.vx vd, vs2, rs1
-VI_VVX_ULOOP_AVG(rs1, +, false);
+VI_VX_ULOOP_AVG(+);
diff --git a/riscv/insns/vasub_vv.h b/riscv/insns/vasub_vv.h
index a45c18db..7dfbdfcf 100644
--- a/riscv/insns/vasub_vv.h
+++ b/riscv/insns/vasub_vv.h
@@ -1,2 +1,2 @@
 // vasub.vv vd, vs2, vs1
-VI_VVX_LOOP_AVG(vs1, -, true);
+VI_VV_LOOP_AVG(-);
diff --git a/riscv/insns/vasub_vx.h b/riscv/insns/vasub_vx.h
index 4e8dba1c..185fa9c1 100644
--- a/riscv/insns/vasub_vx.h
+++ b/riscv/insns/vasub_vx.h
@@ -1,2 +1,2 @@
 // vasub.vx vd, vs2, rs1
-VI_VVX_LOOP_AVG(rs1, -, false);
+VI_VX_LOOP_AVG(-);
diff --git a/riscv/insns/vasubu_vv.h b/riscv/insns/vasubu_vv.h
index 8e2be01a..902fef99 100644
--- a/riscv/insns/vasubu_vv.h
+++ b/riscv/insns/vasubu_vv.h
@@ -1,2 +1,2 @@
 // vasubu.vv vd, vs2, vs1
-VI_VVX_ULOOP_AVG(vs1, -, true);
+VI_VV_ULOOP_AVG(-);
diff --git a/riscv/insns/vasubu_vx.h b/riscv/insns/vasubu_vx.h
index 3cc9ca8a..874dc59e 100644
--- a/riscv/insns/vasubu_vx.h
+++ b/riscv/insns/vasubu_vx.h
@@ -1,2 +1,2 @@
 // vasubu.vx vd, vs2, rs1
-VI_VVX_ULOOP_AVG(rs1, -, false);
+VI_VX_ULOOP_AVG(-);