From 7b3d88f5de4e47c989e64d49498233ecda928b09 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Mon, 13 Apr 2020 01:21:20 -0700 Subject: [PATCH] rvv: add vfslide1[down|up].vf and refine checking rule 1. new features in spec 0.9 2. also fix destination commitlog information for integer comparison Signed-off-by: Chih-Min Chao --- riscv/decode.h | 9 +++++++++ riscv/encoding.h | 6 ++++++ riscv/insns/vfslide1down_vf.h | 28 ++++++++++++++++++++++++++++ riscv/insns/vfslide1up_vf.h | 28 ++++++++++++++++++++++++++++ riscv/insns/vslide1down_vx.h | 13 +++++-------- riscv/insns/vslide1up_vx.h | 14 +++++--------- riscv/insns/vslidedown_vi.h | 5 +---- riscv/insns/vslidedown_vx.h | 5 +---- riscv/insns/vslideup_vi.h | 6 +----- riscv/insns/vslideup_vx.h | 6 +----- riscv/riscv.mk.in | 2 ++ spike_main/disasm.cc | 2 ++ 12 files changed, 89 insertions(+), 35 deletions(-) create mode 100644 riscv/insns/vfslide1down_vf.h create mode 100644 riscv/insns/vfslide1up_vf.h diff --git a/riscv/decode.h b/riscv/decode.h index e1cc414b..9855580b 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -506,6 +506,15 @@ static inline bool is_overlapped(const int astart, const int asize, require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ require(P.VU.vstart == 0); \ +#define VI_CHECK_SLIDE(is_over) \ + require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ + require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ + if (insn.v_vm() == 0 && P.VU.vlmul > 1) \ + require(insn.rd() != 0); \ + if (is_over) \ + require(insn.rd() != insn.rs2()); \ + + // // vector: loop header and end helper // diff --git a/riscv/encoding.h b/riscv/encoding.h index c052c6fe..584bc272 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -932,6 +932,10 @@ #define MASK_VFSGNJN_VF 0xfc00707f #define MATCH_VFSGNJX_VF 0x28005057 #define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f #define MATCH_VFMV_S_F 0x42005057 #define MASK_VFMV_S_F 0xfff0707f #define MATCH_VFMERGE_VFM 0x5c005057 @@ -2209,6 +2213,8 @@ DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) diff --git a/riscv/insns/vfslide1down_vf.h b/riscv/insns/vfslide1down_vf.h new file mode 100644 index 00000000..43fedb0d --- /dev/null +++ b/riscv/insns/vfslide1down_vf.h @@ -0,0 +1,28 @@ +//vfslide1down.vf vd, vs2, rs1 +VI_CHECK_SLIDE(false); + +VI_VFP_LOOP_BASE +if (i != vl - 1) { + switch (P.VU.vsew) { + case e32: { + VI_XI_SLIDEDOWN_PARAMS(e32, 1); + vd = vs2; + } + break; + case e64: { + VI_XI_SLIDEDOWN_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (P.VU.vsew) { + case e32: + P.VU.elt(rd_num, vl - 1, true) = f32(FRS1); + break; + case e64: + P.VU.elt(rd_num, vl - 1, true) = f64(FRS1); + break; + } +} +VI_VFP_LOOP_END diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h new file mode 100644 index 00000000..e0174d65 --- /dev/null +++ b/riscv/insns/vfslide1up_vf.h @@ -0,0 +1,28 @@ +//vfslide1up.vf vd, vs2, rs1 +VI_CHECK_SLIDE(true); + +VI_VFP_LOOP_BASE +if (i != 0) { + switch (P.VU.vsew) { + case e32: { + VI_XI_SLIDEUP_PARAMS(e32, 1); + vd = vs2; + } + break; + case e64: { + VI_XI_SLIDEUP_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (P.VU.vsew) { + case e32: + P.VU.elt(rd_num, 0, true) = f32(FRS1); + break; + case e64: + P.VU.elt(rd_num, 0, true) = f64(FRS1); + break; + } +} +VI_VFP_LOOP_END diff --git a/riscv/insns/vslide1down_vx.h b/riscv/insns/vslide1down_vx.h index 04e25405..e867722f 100644 --- a/riscv/insns/vslide1down_vx.h +++ b/riscv/insns/vslide1down_vx.h @@ -1,8 +1,5 @@ //vslide1down.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -if (P.VU.vlmul > 1 && insn.v_vm() == 0) - require(insn.rd() != 0); +VI_CHECK_SLIDE(false); VI_LOOP_BASE if (i != vl - 1) { @@ -31,16 +28,16 @@ if (i != vl - 1) { } else { switch (sew) { case e8: - P.VU.elt(rd_num, vl - 1) = RS1; + P.VU.elt(rd_num, vl - 1, true) = RS1; break; case e16: - P.VU.elt(rd_num, vl - 1) = RS1; + P.VU.elt(rd_num, vl - 1, true) = RS1; break; case e32: - P.VU.elt(rd_num, vl - 1) = RS1; + P.VU.elt(rd_num, vl - 1, true) = RS1; break; default: - P.VU.elt(rd_num, vl - 1) = RS1; + P.VU.elt(rd_num, vl - 1, true) = RS1; break; } } diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 5154259e..33cb9ed6 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -1,9 +1,5 @@ //vslide1up.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0 && P.VU.vlmul > 1) - require(insn.rd() != 0); +VI_CHECK_SLIDE(true); VI_LOOP_BASE if (i != 0) { @@ -22,13 +18,13 @@ if (i != 0) { } } else { if (sew == e8) { - P.VU.elt(rd_num, 0) = RS1; + P.VU.elt(rd_num, 0, true) = RS1; } else if(sew == e16) { - P.VU.elt(rd_num, 0) = RS1; + P.VU.elt(rd_num, 0, true) = RS1; } else if(sew == e32) { - P.VU.elt(rd_num, 0) = RS1; + P.VU.elt(rd_num, 0, true) = RS1; } else if(sew == e64) { - P.VU.elt(rd_num, 0) = RS1; + P.VU.elt(rd_num, 0, true) = RS1; } } VI_LOOP_END diff --git a/riscv/insns/vslidedown_vi.h b/riscv/insns/vslidedown_vi.h index dd58c1eb..bc440cf2 100644 --- a/riscv/insns/vslidedown_vi.h +++ b/riscv/insns/vslidedown_vi.h @@ -1,8 +1,5 @@ // vslidedown.vi vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -if (P.VU.vlmul > 1 && insn.v_vm() == 0) - require(insn.rd() != 0); +VI_CHECK_SLIDE(false); const reg_t sh = insn.v_zimm5(); VI_LOOP_BASE diff --git a/riscv/insns/vslidedown_vx.h b/riscv/insns/vslidedown_vx.h index 744a7a56..074aa508 100644 --- a/riscv/insns/vslidedown_vx.h +++ b/riscv/insns/vslidedown_vx.h @@ -1,8 +1,5 @@ //vslidedown.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -if (P.VU.vlmul > 1 && insn.v_vm() == 0) - require(insn.rd() != 0); +VI_CHECK_SLIDE(false); const uint128_t sh = RS1; VI_LOOP_BASE diff --git a/riscv/insns/vslideup_vi.h b/riscv/insns/vslideup_vi.h index 99d30bc9..42657892 100644 --- a/riscv/insns/vslideup_vi.h +++ b/riscv/insns/vslideup_vi.h @@ -1,9 +1,5 @@ // vslideup.vi vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0 && P.VU.vlmul > 1) - require(insn.rd() != 0); +VI_CHECK_SLIDE(true); const reg_t offset = insn.v_zimm5(); VI_LOOP_BASE diff --git a/riscv/insns/vslideup_vx.h b/riscv/insns/vslideup_vx.h index 2d68a394..720d2ab5 100644 --- a/riscv/insns/vslideup_vx.h +++ b/riscv/insns/vslideup_vx.h @@ -1,9 +1,5 @@ //vslideup.vx vd, vs2, rs1 -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0 && P.VU.vlmul > 1) - require(insn.rd() != 0); +VI_CHECK_SLIDE(true); const reg_t offset = RS1; VI_LOOP_BASE diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 757c734a..bbcba5ee 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -565,6 +565,8 @@ riscv_insn_ext_v_alu_fp = \ vfsgnjx_vf \ vfsgnjx_vv \ vfsqrt_v \ + vfslide1down_vf \ + vfslide1up_vf \ vfsub_vf \ vfsub_vv \ vfwadd_vf \ diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 50f8b37f..8b9c985e 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -1077,6 +1077,8 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV_VF_INSN(vfsgnjx); DISASM_INSN("vfmv.f.s", vfmv_f_s, 0, {&frd, &vs2}); DISASM_INSN("vfmv.s.f", vfmv_s_f, mask_vfmv_s_f, {&vd, &frs1}); + DISASM_OPIV__F_INSN(vfslide1up); + DISASM_OPIV__F_INSN(vfslide1down); //0b01_0000 DISASM_INSN("vfmerge.vfm", vfmerge_vfm, 0, {&vd, &vs2, &frs1, &v0});