From 79ac5e936854fb65cc790fc71e8c769fd7159e4c Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 6 Apr 2026 15:46:22 -0700
Subject: [PATCH] Correctly check for misalignment on SC/AMO

---
 riscv/mmu.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index e2ca0f03..8a61ad14 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -377,8 +377,9 @@ void mmu_t::store_slow_path(reg_t original_addr, std::size_t len,
     auto [tlb_hit, host_addr, paddr] = access_tlb(tlb_store, original_addr, TLB_FLAGS & ~TLB_CHECK_TRIGGERS);
     bool intrapage = (original_addr % PGSIZE) + len <= PGSIZE;
     bool aligned = (original_addr & (len - 1)) == 0;
+    bool misaligned_ok = !require_alignment && intrapage && is_misaligned_enabled();
 
-    if (likely(tlb_hit && (aligned || (intrapage && is_misaligned_enabled())))) {
+    if (likely(tlb_hit && (aligned || misaligned_ok))) {
       if (actually_store)
         perform_intrapage_store(original_addr, host_addr, paddr, len, bytes, xlate_flags);
       return;