@ -11,8 +11,7 @@ switch(insn.rtype.rs2)
break;
case 29:
val = tid;
throw trap_illegal_instruction;
default:
val = -1;
@ -5,6 +5,5 @@ switch(insn.rtype.rs2)
tid = RS1;
}
@ -19,7 +19,6 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
epc = 0;
badvaddr = 0;
cause = 0;
tid = 0;
pcr_k0 = 0;
pcr_k1 = 0;
tohost = 0;
@ -39,7 +39,6 @@ private:
uint32_t interrupts_pending;
// unprivileged control registers
uint32_t tid;
uint32_t fsr;
// 32-bit or 64-bit mode (redundant with sr)