vector: crypto: fix overlap check when EGW > VLEN

riscv/insns/vsm4r_vs.h

@@ -7,7 +7,7 @@ const uint32_t EGS = 4;
 require_vsm4_constraints;
 require_align(insn.rd(), P.VU.vflmul);
 // No overlap of vd and vs2.
-require_noover(insn.rs2(), 1, insn.rd(), P.VU.vflmul);
+require_noover_eglmul(insn.rd(), insn.rs2());
 
 VI_ZVK_VD_VS2_NOOPERANDS_PRELOOP_EGU32x4_NOVM_LOOP(
   {},

riscv/zvk_ext_macros.h

@@ -86,6 +86,18 @@
 //    (LMUL * VLEN) <= EGW
 #define require_egw_fits(EGW)  require((EGW) <= (P.VU.VLEN * P.VU.vflmul))
 
+// ensure that rs2 and rd do not overlap, assuming rd encodes an LMUL wide
+// vector register group and rs2 encodes an vs2_EMUL=ceil(EGW / VLEN) vector register
+// group.
+// Assumption: LMUL >= vs2_EMUL which is enforced independently through require_egw_fits.
+#define require_noover_eglmul(vd, vs2) \
+  do { \
+    int vd_emul = P.VU.vflmul < 1.f ? 1 : (int) P.VU.vflmul; \
+    int aligned_vd = vd / vd_emul; \
+    int aligned_vs2 = vs2 / vd_emul; \
+    require(aligned_vd != aligned_vs2); \
+  } while (0)
+
 // Checks that the vector unit state (vtype and vl) can be interpreted
 // as element groups with EEW=32, EGS=4 (four 32-bits elements per group),
 // for an effective element group width of EGW=128 bits.

riscv/zvkned_ext_macros.h

@@ -2,6 +2,7 @@
 // the RISC-V Zvkned extension (vector AES single round).
 
 #include "insns/aes_common.h"
+#include "zvk_ext_macros.h"
 
 #ifndef RISCV_ZVKNED_EXT_MACROS_H_
 #define RISCV_ZVKNED_EXT_MACROS_H_
@@ -21,7 +22,7 @@
     require(P.VU.vsew == 32); \
     require_egw_fits(128); \
     require_align(insn.rd(), P.VU.vflmul); \
-    require_noover(insn.rs2(), 1, insn.rd(), P.VU.vflmul); \
+    require_noover_eglmul(insn.rd(), insn.rs2()); \
   } while (false)
 
 // vaes*.vv instruction constraints. Those are the same as the .vs ones,