op: hyperviosr: fix exception code and name

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/encoding.h

@@ -2128,8 +2128,8 @@
 #define CAUSE_MISALIGNED_STORE 0x6
 #define CAUSE_STORE_ACCESS 0x7
 #define CAUSE_USER_ECALL 0x8
-#define CAUSE_HYPERVISOR_ECALL 0x9
-#define CAUSE_SUPERVISOR_ECALL 0xa
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa
 #define CAUSE_MACHINE_ECALL 0xb
 #define CAUSE_FETCH_PAGE_FAULT 0xc
 #define CAUSE_LOAD_PAGE_FAULT 0xd
@@ -3211,8 +3211,8 @@ DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
 DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
-DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL)
 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
 DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
 DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)

riscv/insns/ecall.h

@@ -3,9 +3,9 @@ switch (STATE.prv)
   case PRV_U: throw trap_user_ecall();
   case PRV_S:
     if (STATE.v)
-      throw trap_supervisor_ecall();
+      throw trap_virtual_supervisor_ecall();
     else
-      throw trap_hypervisor_ecall();
+      throw trap_supervisor_ecall();
   case PRV_M: throw trap_machine_ecall();
   default: abort();
 }

riscv/trap.h

@@ -82,7 +82,7 @@ DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)
 DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault)
 DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall)
 DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall)
-DECLARE_TRAP(CAUSE_HYPERVISOR_ECALL, hypervisor_ecall)
+DECLARE_TRAP(CAUSE_VIRTUAL_SUPERVISOR_ECALL, virtual_supervisor_ecall)
 DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall)
 DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault)
 DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault)