Simplfy vfcvt

riscv/decode.h

@@ -2389,6 +2389,40 @@ reg_t index[P.VU.vlmax]; \
   set_fp_exceptions; \
   VI_VFP_LOOP_END
 
+#define VI_VFP_CVT_INT_TO_FP(BODY16, BODY32, BODY64, sign) \
+  VI_CHECK_SDS(false); \
+  switch(P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 16, sign), {}, BODY16); } \
+      break; \
+    case e32: \
+      { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 32, sign), {}, BODY32); } \
+      break; \
+    case e64: \
+      { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 64, sign), {}, BODY64); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
+#define VI_VFP_CVT_FP_TO_INT(BODY16, BODY32, BODY64, sign) \
+  VI_CHECK_SDS(false); \
+  switch(P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 16, sign), {}, BODY16); } \
+      break; \
+    case e32: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 32, sign), {}, BODY32); } \
+      break; \
+    case e64: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 64, sign), {}, BODY64); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
 #define VI_VFP_NCVT_FP_TO_FP(BODY8, BODY16, BODY32, \
                             CHECK8, CHECK16, CHECK32) \
   VI_CHECK_SDS(false); \

riscv/insns/vfcvt_f_x_v.h

@@ -1,14 +1,7 @@
 // vfcvt.f.x.v vd, vd2, vm
-VI_VFP_VF_LOOP
-({
-  auto vs2_i = P.VU.elt<int16_t>(rs2_num, i);
-  vd = i32_to_f16(vs2_i);
-},
-{
-  auto vs2_i = P.VU.elt<int32_t>(rs2_num, i);
-  vd = i32_to_f32(vs2_i);
-},
-{
-  auto vs2_i = P.VU.elt<int64_t>(rs2_num, i);
-  vd = i64_to_f64(vs2_i);
-})
+VI_VFP_CVT_INT_TO_FP(
+  { vd = i32_to_f16(vs2); }, // BODY16
+  { vd = i32_to_f32(vs2); }, // BODY32
+  { vd = i64_to_f64(vs2); }, // BODY64
+  int                        // sign
+)

riscv/insns/vfcvt_f_xu_v.h

@@ -1,14 +1,7 @@
 // vfcvt.f.xu.v vd, vd2, vm
-VI_VFP_VF_LOOP
-({
-  auto vs2_u = P.VU.elt<uint16_t>(rs2_num, i);
-  vd = ui32_to_f16(vs2_u);
-},
-{
-  auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i);
-  vd = ui32_to_f32(vs2_u);
-},
-{
-  auto vs2_u = P.VU.elt<uint64_t>(rs2_num, i);
-  vd = ui64_to_f64(vs2_u);
-})
+VI_VFP_CVT_INT_TO_FP(
+  { vd = ui32_to_f16(vs2); }, // BODY16
+  { vd = ui32_to_f32(vs2); }, // BODY32
+  { vd = ui64_to_f64(vs2); }, // BODY64
+  uint                        // sign
+)

riscv/insns/vfcvt_rtz_x_f_v.h

@@ -1,11 +1,7 @@
 // vfcvt.rtz.x.f.v vd, vd2, vm
-VI_VFP_VF_LOOP
-({
-  P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true);
-},
-{
-  P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true);
-},
-{
-  P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true);
-})
+VI_VFP_CVT_FP_TO_INT(
+  { vd = f16_to_i16(vs2, softfloat_round_minMag, true); }, // BODY16
+  { vd = f32_to_i32(vs2, softfloat_round_minMag, true); }, // BODY32
+  { vd = f64_to_i64(vs2, softfloat_round_minMag, true); }, // BODY64
+  int                                                      // sign
+)

riscv/insns/vfcvt_rtz_xu_f_v.h

@@ -1,11 +1,7 @@
 // vfcvt.rtz.xu.f.v vd, vd2, vm
-VI_VFP_VF_LOOP
-({
-  P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true);
-},
-{
-  P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true);
-},
-{
-  P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true);
-})
+VI_VFP_CVT_FP_TO_INT(
+  { vd = f16_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY16
+  { vd = f32_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY32
+  { vd = f64_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY64
+  uint                                                      // sign
+)

riscv/insns/vfcvt_x_f_v.h

@@ -1,11 +1,7 @@
 // vfcvt.x.f.v vd, vd2, vm
-VI_VFP_VF_LOOP
-({
-  P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm->read(), true);
-},
-{
-  P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm->read(), true);
-},
-{
-  P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm->read(), true);
-})
+VI_VFP_CVT_FP_TO_INT(
+  { vd = f16_to_i16(vs2, softfloat_roundingMode, true); }, // BODY16
+  { vd = f32_to_i32(vs2, softfloat_roundingMode, true); }, // BODY32
+  { vd = f64_to_i64(vs2, softfloat_roundingMode, true); }, // BODY64
+  int                                                      // sign
+)

riscv/insns/vfcvt_xu_f_v.h

@@ -1,11 +1,7 @@
 // vfcvt.xu.f.v vd, vd2, vm
-VI_VFP_VV_LOOP
-({
-  P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm->read(), true);
-},
-{
-  P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm->read(), true);
-},
-{
-  P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, STATE.frm->read(), true);
-})
+VI_VFP_CVT_FP_TO_INT(
+  { vd = f16_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY16
+  { vd = f32_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY32
+  { vd = f64_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY64
+  uint                                                      // sign
+)