Merge pull request #1987 from riscv-software-src/fix-vssra

Fix regression in vssra.vi instruction

riscv/insns/vsra_vi.h

@@ -1,5 +1,5 @@
 // vsra.vi vd, vs2, zimm5
-VI_VI_LOOP
+VI_VI_ULOOP
 ({
-  vd = vs2 >> (simm5 & (sew - 1) & 0x1f);
+  vd = vs2 >> (zimm5 & (sew - 1));
 })

riscv/insns/vssra_vi.h

@@ -1,8 +1,8 @@
-// vssra.vi vd, vs2, simm5
-VI_VI_LOOP
+// vssra.vi vd, vs2, zimm5
+VI_VI_ULOOP
 ({
   VRM xrm = P.VU.get_vround_mode();
-  int sh = simm5 & (sew - 1);
+  int sh = zimm5 & (sew - 1);
   int128_t val = vs2;
 
   INT_ROUNDING(val, xrm, sh);

riscv/insns/vssrl_vi.h

@@ -1,4 +1,4 @@
-// vssra.vi vd, vs2, simm5
+// vssra.vi vd, vs2, zimm5
 VI_VI_ULOOP
 ({
   VRM xrm = P.VU.get_vround_mode();