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@ -1405,8 +1405,6 @@ VI_VX_ULOOP({ \ |
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#define VI_EXT_CHECK(div) \ |
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require(insn.rd() != insn.rs2()); \ |
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require_vm; \ |
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reg_t from = P.VU.vsew / div; \ |
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require(from >= e8 && from <= e64); \ |
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require(((float)P.VU.vflmul / div) >= 0.125 && ((float)P.VU.vflmul / div) <= 8 ); \ |
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require_align(insn.rd(), P.VU.vflmul); \ |
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require_align(insn.rs2(), P.VU.vflmul / div); \ |
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@ -1418,6 +1416,8 @@ VI_VX_ULOOP({ \ |
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// vector: sign/unsiged extension
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#define VI_VV_EXT(div, type) \ |
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reg_t from = P.VU.vsew / div; \ |
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require(from >= e8 && from <= e64); \ |
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VI_EXT_CHECK(div); \ |
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VI_LOOP_BASE \ |
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reg_t pat = (((P.VU.vsew >> 3) << 4) | from >> 3); \ |
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